Design Engineer (8007)

TSMC•West Covina, CA

2d•$155,896 - $156,000

About The Position

The Design Engineer is responsible for design rule checking, layout-versus-schematic checking, and resolving PDV, EMIR, noise, and signal electromigration violations and errors. The role may include customizing and implementing top-level clocks and implementing timing ECOs on high-performance blocks. The position performs DRC/LVS/ERC/antenna analysis and cleanup; floorplan analysis and congestion resolution; power IR/EM and signal EM/noise analysis and fixes; physical verification signoff; timing-closure ECO implementation; and customized clock-tree structuring. It also involves maintaining thorough documentation of processes, methodologies, and solutions, and sharing knowledge and best practices with the team. The work site is TSMC Technology, Inc., 2851 Junction Avenue, San Jose, California 95134, as well as various unanticipated work locations.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field of study.
Experience in research projects or an internship related to RTL coding, digital design and testing, physical implementation, or design verification.
Experience programming in Perl/TCL.
Experience with complete Netlist-GDS P&R and signoff tasks.
Experience in block-level implementation or chip integration and signoff.
Knowledge of hardware design courses including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
Knowledge of major EDA tools and design flows.
Knowledge of advanced technology, chip-level integration, wire editing, and low-power implementation methodology.

Responsibilities

Perform design rule check (DRC) and layout-versus-schematic (LVS) checking.
Resolve PDV, EMIR, noise, and signal electromigration violations and errors.
Perform DRC/LVS/ERC/antenna analysis and cleanup.
Analyze floorplans and resolve congestion.
Analyze and fix power IR/EM issues.
Analyze and fix signal EM/noise issues.
Perform physical verification signoff.
Implement ECOs for timing closure.
Customize clock-tree structures and, as applicable, customize and implement top-level clocks.
Maintain thorough documentation of processes, methodologies, and solutions.
Share knowledge and best practices with the team to foster collaboration and improve efficiency.