Design Engineer (8007)

TSMC•San Jose, CA

About The Position

The Design Engineer is responsible for design rule checking, layout-versus-schematic checking, and resolving PDV, EMIR, noise, and signal-EM violations and errors. The role may include customizing and implementing top clocks and implementing timing ECOs on high-performance blocks. The position covers DRC/LVS/ERC/antenna analysis and cleanup, floorplan analysis and congestion resolution, power IR/EM analysis and fixes, signal EM/noise analysis and fixes, physical verification signoff, timing-closure ECOs, and customized clock-tree structures. The engineer also maintains thorough documentation of processes, methodologies, and solutions and shares knowledge and best practices with the team. The listed work site is TSMC Technology, Inc., 2851 Junction Avenue, San Jose, California 95134, and various unanticipated work locations. The posted annual salary range is $155,896 to $156,000. Pay may vary based on skills, qualifications, education, experience, position level, and location. TSMC describes its total compensation package as including market-competitive pay, allowances, bonuses, comprehensive benefits, and development opportunities.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field of study.
Experience in research projects or an internship related to RTL coding, digital design and testing, physical implementation, or design verification.
Experience with Perl/TCL programming.
Experience with complete Netlist-GDS P&R and signoff tasks.
Experience in block-level implementation or chip integration and signoff.
Knowledge of hardware design courses, including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
Knowledge of major EDA tools and design flows.
Knowledge of advanced technology, chip-level integration, wire editing, and low-power implementation methodology.

Responsibilities

Perform design rule checking and layout-versus-schematic checking, and resolve PDV, EMIR, noise, and signal-EM violations and errors.
Perform DRC/LVS/ERC/antenna analysis and cleanup.
Analyze floorplans and resolve congestion.
Perform power IR/EM analysis and implement fixes.
Perform signal EM/noise analysis and implement fixes.
Complete physical verification signoff.
Implement ECOs for timing closure.
Customize clock-tree structures; the role may include customization and implementation of top clocks.
Maintain thorough documentation of processes, methodologies, and solutions.
Share knowledge and best practices with the team to support collaboration and efficiency.