Design Engineer (8007)

TSMC•San Jose, CA

3d•$155,896 - $156,000

About The Position

The Design Engineer is responsible for design rule checking, layout-versus-schematic checking, and resolving PDV, EMIR, noise, and signal EM violations and errors. The role may involve customization and implementation of top clocks and timing ECOs on high-performance blocks. The position includes DRC/LVS/ERC/antenna analysis and cleanup; floorplan analysis and congestion solutions; power IR/EM and signal EM/noise analysis and fixes; physical verification signoff; timing-closure ECO implementation; and customized clock-tree structures. The engineer also maintains thorough documentation of processes, methodologies, and solutions and shares knowledge and best practices with the team to support collaboration and efficiency. The work site is TSMC Technology, Inc. in San Jose, California, and various unanticipated work locations. The posted annual salary range is $155,896 to $156,000.

Requirements

Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, or a related field of study.
Experience in research projects or an internship related to RTL coding, digital design and testing, physical implementation, or design verification.
Experience programming in Perl/TCL.
Experience with complete Netlist-GDS place-and-route and signoff tasks.
Experience in block-level implementation or chip integration and signoff.
Knowledge of hardware design subjects including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
Knowledge of major EDA tools and design flows.
Knowledge of advanced technology, chip-level integration, wire editing, and low-power implementation methodology.

Responsibilities

Perform design rule checking and layout-versus-schematic checking, and resolve PDV/EMIR/noise/signal EM violations and errors.
Conduct DRC/LVS/ERC/antenna analysis and cleanup.
Analyze floorplans and develop solutions to congestion.
Analyze and resolve power IR/EM and signal EM/noise issues.
Perform physical verification signoff.
Implement ECOs for timing closure.
Customize clock-tree structures and, as needed, implement top clocks and timing ECOs on high-performance blocks.
Maintain documentation of processes, methodologies, and solutions.
Share knowledge and best practices with the team.