Design Engineer (7670)
About The Position
Responsible for the entire APR implementation flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PDV/EMIR/Noise/SigEM cleaup and signoff on lower power SoC blocks. Specific duties include: Completing entire physical implementation of the block level and tape-out production chip; Block level floorplan with the ability to analyze the quality of the floorplan; Customized Clock tree structure and Place & Route; Implementing ECOs for timing closure; Performing signal EM/Noise and Power IR/EM analysis and fix; Completing DRC/LVS/ERC/ANTENNA analysis and clean up; and Performing physical verification sign off.
Requirements
- Netlist (or RTL)-GDS physical implementation experience
- Experience with advanced technology and design rule
- Experience in block level implementation or chip integration and signoff
- Experience in Perl/TCL/Python/C++ language programming
- Knowledge of PnR algorithm, logic synthesis, and design for test
- Knowledge of major EDA tools/design flows (e.g. Cadence Innovus and Simens Calibre)
Responsibilities
- Completing entire physical implementation of the block level and tape-out production chip
- Block level floorplan with the ability to analyze the quality of the floorplan
- Customized Clock tree structure and Place & Route
- Implementing ECOs for timing closure
- Performing signal EM/Noise and Power IR/EM analysis and fix
- Completing DRC/LVS/ERC/ANTENNA analysis and clean up
- Performing physical verification sign off
Benefits
- market competitive pay
- allowances
- bonuses
- comprehensive benefits
- extensive development opportunities and programs
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What This Job Offers
Job Type
Full-time
Career Level
Senior
