Design Engineer (8008)
TSMC•San Jose, CA
•$155,896 - $158,000
About The Position
The Design Engineer is responsible for design rule checks, layout-versus-schematic checks, and resolving PDV, EMIR, noise, and signal electromigration violations and errors. The role involves customizing and implementing top-level clocks and timing engineering change orders (ECOs) on high-performance blocks. The position is based at TSMC Technology, Inc. in San Jose, California, and may also involve various unanticipated work locations.
Requirements
- Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
- Knowledge of hardware design, including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
- Knowledge of major EDA tools and design flows, including Cadence Innovus, Cadence Virtuoso, Tempus, and Design Compiler (DC).
- Experience in RTL coding, digital design and testing, and physical implementation.
- Experience with Perl/TCL programming.
- Experience with N16-and-below technology, chip-level integration, wire editing, and low-power implementation methodology.
- Experience with Netlist-GDS place-and-route and signoff tasks.
- Experience in block-level implementation or chip integration and signoff.
Responsibilities
- Perform DRC, LVS, ERC, and antenna analysis and cleanup.
- Analyze floorplans and resolve congestion.
- Analyze and fix power IR and EM issues.
- Analyze and fix signal EM and noise issues.
- Complete physical verification signoff.
- Implement ECOs for timing closure.
- Customize clock tree structures.
- Perform floorplanning, placement, and routing.
Benefits
- Market-competitive pay
- Allowances
- Bonuses
- Comprehensive benefits
- Extensive development opportunities and programs
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What This Job Offers
Job Type
Full-time
