Design Engineer (8008)

TSMC • West Covina, CA

5h • $155,896 - $158,000 • Onsite

About The Position

The Design Engineer is responsible for design rule checking, layout-versus-schematic checking, and resolving PDV/EMIR/Noise/SigEM violations and errors. The role performs customization and implementation of top clocks and timing ECOs on high-performance blocks. Work is performed at TSMC Technology, Inc., 2851 Junction Avenue, San Jose, California, and at various unanticipated work locations.

Requirements

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field.
• Knowledge of hardware design, including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
• Knowledge of major EDA tools and design flows, including Cadence Innovus, Cadence Virtuoso, Tempus, and Design Compiler (DC).
• Experience in RTL coding, digital design and testing, and physical implementation.
• Experience programming in Perl and TCL.
• Experience with N16 and below technology, chip-level integration, wire editing, and low-power implementation methodology.
• Experience with Netlist-GDS P&R and sign-off tasks.
• Experience in block-level implementation or chip integration and sign-off.

Responsibilities

• Perform DRC/LVS/ERC/antenna analysis and cleanup.
• Analyze floorplans and resolve congestion.
• Analyze and fix power IR/EM issues.
• Analyze and fix signal EM/noise issues.
• Perform physical verification sign-off.
• Implement ECOs for timing closure.
• Customize clock-tree structures.
• Perform floorplanning, placement, and routing.
• Customize and implement top clocks and timing ECOs on high-performance blocks.
• Resolve PDV/EMIR/Noise/SigEM violations and errors.

Benefits

• Market-competitive pay, allowances, bonuses, and comprehensive benefits.
• Extensive development opportunities and programs.

What This Job Offers

• Job Type: Full-time