Design Engineer (8008)

TSMC•San Jose, CA

11d•Onsite

About The Position

The Design Engineer is responsible for design rule checking, layout-versus-schematic checking, and resolving PDV, EMIR, noise, and signal electromigration violations and errors. The role includes customizing and implementing top-level clocks and timing ECOs on high-performance blocks. The position performs physical-design verification, floorplan analysis, congestion resolution, power-integrity and signal-integrity analysis, physical verification signoff, timing-closure ECO implementation, clock-tree customization, and floorplanning, placement, and routing.

Requirements

Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering, or a related field of study.
Knowledge of hardware design, including VLSI design, digital integrated circuits, logic design, design for testing, computer architecture, and digital design automation.
Knowledge of major EDA tools and design flows, including Cadence Innovus, Cadence Virtuoso, Tempus, and Design Compiler (DC).
Experience in RTL coding, digital design and testing, and physical implementation.
Experience programming in Perl and TCL.
Experience with N16 and below technology, chip-level integration, wire editing, and low-power implementation methodology.
Experience with Netlist-GDS P&R and signoff tasks.
Experience in block-level implementation or chip integration and signoff.

Responsibilities

Perform DRC/LVS/ERC/antenna analysis and cleanup.
Analyze floorplans and resolve congestion.
Analyze and fix power IR/EM issues.
Analyze and fix signal EM/noise issues.
Perform physical verification signoff.
Implement ECOs for timing closure.
Customize clock-tree structures.
Perform floorplanning, placement, and routing.
Customize and implement top-level clocks and timing ECOs on high-performance blocks.
Perform design rule checks and layout-versus-schematic checks, and fix PDV/EMIR/noise/signal-EM violations and errors.