Design Engineer II

Cadence Design Systems•Austin, TX
•Onsite

About The Position

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. This person will work with the existing functional verification environment to add new features into the verification environment, ensuring various customer configurations are clean as part of verification regressions, supporting customers in case of any issues with using the verification environment, and functional and code coverage. Additionally, this person will be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics. As a Verification Engineer for Memory Controller development team, you will lead the verification effort and contribute to the functional verification of the Cadence's Memory Controller IP. We’re doing work that matters. Help us solve what others can’t.

Requirements

  • BS/MS - Electrical / Computer Engineering
  • At least 2-3 years of relevant experience including design verification experience.
  • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must.
  • UVM based functional verification environment development is required.

Nice To Haves

  • AXI and/or CHI-E experience
  • Memory controller verification experience
  • AXI and/or CHI-E, DDR Memory experience is highly desirable.

Responsibilities

  • Add new features into the existing functional verification environment.
  • Ensure various customer configurations are clean as part of verification regressions.
  • Support customers in case of any issues with using the verification environment.
  • Ensure functional and code coverage.
  • Ensure the design is in line with the technical and quality requirements set for the team – particularly with respect to our quality Metrics.
  • Lead the verification effort and contribute to the functional verification of the Cadence's Memory Controller IP.
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