Design Automation Engineer (TFM/EDA)

Intel Corporation•Santa Clara, CA

26d•$100,550 - $194,270•Hybrid

About The Position

Intel Foundry Automation - Government Programs is seeking a Silicon Design Automation Engineer with experience in Design TFM (Tools, Flows, Methodology) and EDA tools support for Intel's PDK for external Foundry customers. The role covers installation, maintenance, and technical support of the design environment—including automation scripts, front-end and back-end design tools, flows, processes, and licenses—and the compute environment, including storage, compute, NetBatch, and ION. The engineer also provides technical support for Intel PDK and collateral. The position supports designers through tapeout, helps teams ramp up through training and documentation, and works with EDA providers, PDK and library experts, flow development teams, product design teams, and EC. The engineer creates automation to simplify design environment installation and supports integration of new tools and methods into existing workflows. The role is eligible for Intel's hybrid work model, with time split between an assigned Intel site and off-site work.

Requirements

US citizenship is required.
Ability to obtain a US Government TS/SCI security clearance.
BS in Electrical or Computer Engineering with at least 1 year of experience, or MS in Electrical or Computer Engineering with at least 2 years of experience, in front-end and back-end design tools and flows.
Experience with EDA tools and methodologies, including debugging and problem-solving.
Experience in physical design, optimization, and tools flows and methodology (TFM).
Experience with Verilog or VHDL and Tcl, Perl, or Python scripting.
Linux experience, including bash and tcsh.

Nice To Haves

Active US Government security clearance at a minimum of Secret level.
Hands-on experience installing industry-standard front-end and back-end EDA tools.
Experience installing foundry PDKs and flows, such as Cheetah.
Experience with debugging and design automation.

Responsibilities

Resolve designers’ tool and methodology issues on the path to tapeout.
Support design ramp-up through training and documentation.
Interact with EDA providers and ensure required tool features are available for projects with high quality.
Partner with PDK and library experts, flow development teams, and product design teams.
Collaborate with EC to provision adequate compute capacity and help debug associated issues.
Create automation, such as scripts and checkers, for installing the design environment, including PDKs, EDA tools, and licenses.
Support integration of new tools and methods into existing design workflows, ensuring seamless adoption and scalability.
Install, maintain, and provide technical support for the design and compute environments and Intel PDK collateral.