CPU/NPU Architecture RTL Design Engineer (Sr level and up)
About The Position
Join us to build IP blocks that power Snapdragon processors and AI inference engines. Qualcomm's Hexagon NPU Team is hiring for the various positions in Markham, Canada for the development of high-performance, energy-efficient CPU and AI processors. Hexagon NPU is an in-house built Qualcomm proprietary processor which is the center of Qualcomm's hybrid AI computing capability targeted for a broad spectrum of AI use cases across market segments. New Position We are seeking highly skilled engineers with: ideally 5+ years of experience strong knowledge in CPU/AI processor micro-architecture, architecture RTL design debug architecture power-management and circuit design. Other areas of expertise should span: RTL Design of high-performance CPU/AI processors RTL coding, micro-architecture and architecture Computer Arithmetic Instruction fetch, scheduling and register renaming Fixed-Point, Floating-Point design Matrix Multiply engines Vector Extensions Memory sub-systems, Load/store, caches, atomics, coherence and consistency Branch prediction, out-of-order, dispatch, schedulers Multi-processor and multi-threaded systems RISC-V Power, performance and Area (PPA) optimizations CPU sub-system Logic Design
Requirements
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field.
- strong knowledge in CPU/AI processor micro-architecture, architecture
- RTL design
- debug architecture
- power-management and circuit design.
- RTL Design of high-performance CPU/AI processors
- RTL coding, micro-architecture and architecture
- Computer Arithmetic
- Instruction fetch, scheduling and register renaming
- Fixed-Point, Floating-Point design
- Matrix Multiply engines
- Vector Extensions
- Memory sub-systems, Load/store, caches, atomics, coherence and consistency
- Branch prediction, out-of-order, dispatch, schedulers
- Multi-processor and multi-threaded systems
- RISC-V
- Power, performance and Area (PPA) optimizations
- CPU sub-system Logic Design
Benefits
- competitive annual discretionary bonus program
- opportunity for annual RSU grants
- highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
5,001-10,000 employees
