CPU Core Design Verification Testbench Lead

Tenstorrent • Austin, TX

8h • Hybrid

About The Position

Tenstorrent is a leader in cutting-edge AI technology, aiming to revolutionize performance, usability, and cost-efficiency. As AI transforms the computing landscape, solutions must integrate innovations in software models, compilers, platforms, networking, and semiconductors. Our team has developed a high-performance RISC-V CPU from scratch and is passionate about AI and building the best AI platform. We foster collaboration, curiosity, and a drive to solve complex problems. We are expanding our team and seeking contributors at all levels. At Tenstorrent, we create open, state-of-the-art compute solutions for real-world applications and developers. This role involves owning CPU core-level testbench development and verification, significantly influencing the behavior of our out-of-order RISC-V CPUs in silicon. This is a hybrid position, available in Austin, TX or Santa Clara, CA. We are open to candidates with various experience levels; the appropriate level will be determined during the interview process and reflected in the offer.

Requirements

• 8+ years in CPU verification, CPU testbench development, or closely related digital design.
• Deep hands-on experience building and owning CPU core-level testbenches, not just using existing environments.
• In-depth knowledge of high-performance out-of-order CPU microarchitecture.
• Comfortable developing testbench infrastructure in CVM methodology.
• Comfortable working across RTL, waveforms, logs, regressions, and cross-functional debug with design, DV, emulation, and post-silicon teams.
• Comfortable using AI-assisted verification workflows to improve debug, stimulus creation, and coverage analysis, while applying strong engineering judgment to validate results.

Nice To Haves

• UVM experience is a strong plus.

Responsibilities

• Lead hands-on CPU core-level testbench development for high-performance out-of-order RISC-V cores.
• Own and evolve CVM-based verification methodology, infrastructure, and reusable testbench components.
• Plan and drive functional verification for CPU core features, ISA behavior, and microarchitectural scenarios.
• Develop UVM, assembly, C/C++ stimulus, and C++ functional models for RISC-V extensions and un-core components such as APIC and IOMMU.
• Debug regressions, close coverage, and improve core, cluster, and chip-level testbenches across simulation, emulation, and post-silicon environments.
• Develop testbench and tooling infrastructure that combines Python orchestration with specialized AI agents to accelerate triage and root-cause analysis across logs, waveforms, and verification databases.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Education Level: No Education Listed