Principal Design Verification Engineer – CPU Core Hardware Prefetch

SiFive•Austin, TX

About The Position

SiFive is looking for a Principal Design Verification Engineer to lead verification strategy and execution for CPU Core Hardware Prefetch in a high-performance out-of-order core. This is a senior tech-lead role for an engineer who can define architecture-aware verification strategy, identify microarchitectural risk early, solve the hardest hardware prefetch verification problems, and raise verification quality across the broader CPU DV organization. The primary technical scope of this role is advanced hardware prefetch verification, with emphasis on prefetch training behavior, stream detection and replacement, request generation, issue-queue behavior, DCache interactions, feedback-driven aggressiveness control, CSR configurability, and functional correctness across block-level and core-level integration contexts. You will work closely with architecture, RTL, performance, software, and verification teams to ensure design intent is captured correctly, risks are identified early, and signoff quality is achieved with strong technical judgment and scalable methodology.

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
12+ years of relevant experience in CPU/core or SoC functional verification, with substantial experience appropriate for a Principal / T6 role.
Direct experience with out-of-order CPU core verification and strong understanding of CPU microarchitecture.
Deep expertise in hardware prefetch verification or closely related CPU memory-subsystem verification, with the ability to translate architectural intent into an effective verification strategy and execution plan.
Strong knowledge of verification flow methodology, including test planning, stimulus generation, failure analysis, coverage analysis, and coverage closure.
Strong debug skills and strong software or scripting fundamentals for building scalable DV infrastructure, automation, and analysis workflows.
Strong understanding of CPU memory behavior, including ordering-sensitive interactions, cache hierarchy effects, and how hardware prefetch interacts with demand traffic and system performance.
8+ years direct experience on memory management verification
Deep understand of computer architecture
Seasoned developer using object oriented programing principles

Nice To Haves

Experience verifying advanced hardware prefetch architectures, such as stride-based or stream-based prefetchers with training, confirmation, throttling, and adaptive distance control.
Experience verifying prefetch engines integrated with DCache or memory-subsystem pipelines, including interactions with issue queues, MSHRs, cache feedback, and replay behavior.
Experience developing or reviewing verification content that uses performance counters, constrained-random traffic, directed corner-case scenarios, and software-driven stress patterns to validate hardware prefetch correctness.
Experience with formal verification to target bounded, control-heavy, or interface-sensitive microarchitectural problems.
Experience using emulation or other acceleration techniques to improve turnaround on large CPU verification workloads.
Experience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.
Demonstrated technical leadership through mentoring, methodology influence, and cross-team execution on complex CPU verification efforts.

Responsibilities

Lead verification planning and execution for CPU hardware prefetch functionality in a high-performance out-of-order core, with ownership spanning unit-level and core-level verification strategy, debug, coverage closure, and signoff readiness.
Define verification strategy, test plans, checkers, scoreboards, assertions, stimulus strategies, and coverage models for advanced hardware prefetch microarchitecture and its corner cases.
Drive verification of hardware prefetch behaviors including stream allocation and replacement, training from demand requests, prefetch generation, request replay and kill behavior, issue-queue interactions, and feedback-driven control of prefetch aggressiveness.
Verify correctness of runtime configurability through hardware prefetch CSRs, including enablement, windowing, initial distance, maximum allowed distance, linear-to-exponential growth thresholds, queue-allocation controls, and thresholds tied to L1/L2 cache and MSHR behavior.
Drive verification of interactions between the hardware prefetch engine and the memory hierarchy, including DCache pipeline behavior, cacheable-read-only training conditions, MSHR fullness backpressure, L1/L2 prefetch targeting, and arbitration with other core-generated traffic.
Develop verification strategies for difficult corner cases such as stream misconfirmation and untraining, queue unavailability, threshold-triggered throttling, page-boundary behavior, multi-stream behavior, and correctness under diverse operating modes and software-programmed configurations.
Use architectural counters, self-checking tests, and microarchitectural observability to validate that prefetch behavior is both functionally correct and robust across realistic performance-sensitive traffic patterns.
Partner with architects and designers from early feature-definition stages to review specifications, identify ambiguity, improve debugability, and influence the design from a verification perspective.
Apply the right verification method for the problem, including simulation, formal techniques, emulation, and performance-oriented validation where appropriate for high-risk or hard-to-observe hardware prefetch behaviors.
Drive efficient failure analysis and root-cause debug across specification, RTL, test content, assertions, and verification infrastructure.
Mentor engineers across the organization and shape reusable verification approaches, infrastructure, and methodology for future CPU core generations.