Design Verification Lead

Advanced Micro Devices, Inc•San Jose, CA

2d•Hybrid

About The Position

As a Design Verification Engineer Lead in the AECG Group, you will help bring to life cutting-edge FPGA and ASIC solutions for a broad range of customers. As a member of the front-end design and integration team, you will collaborate closely with architecture, IP design, physical design, firmware, and product engineering teams to deliver first-pass silicon success for next-generation PCIe and CXL-based IP solutions.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Minimum 10 years of design verification experience using UVM methodology.
ASIC/IP verification experience using UVM methodology.
Strong expertise in SystemVerilog, Verilog, object-oriented programming, and UVM-based verification environments.
Experience verifying high-speed protocols such as PCIe, CXL, Ethernet, PCIe Gen6, or 400G Ethernet.
Proficiency in scripting and automation using Python, Perl, or similar languages.
Experience working across the ASIC/FPGA development lifecycle from planning through tape-out.
Technical leadership, mentoring experience, and strong communication skills within geographically distributed teams.

Nice To Haves

Exposure to performance verification, simulation optimization, acceleration technologies, HLS tools, or verification efficiency improvements.
Knowledge of computer architecture, system-level design concepts, and emerging AI-driven verification methodologies is a plus.

Responsibilities

Collaborate with architects, hardware designers, and firmware teams to define and verify new PCIe, CXL, and high-speed connectivity features.
Develop comprehensive verification plans that address feature interactions, hardware/software integration, performance requirements, and system-level use cases.
Design and implement IP or subsystem-level UVM verification environments, including monitors, scoreboards, checkers, and reusable verification components.
Develop directed and constrained-random tests, execute regressions, and debug failures to ensure high functional coverage and design quality.
Drive verification automation, methodology improvements, and adoption of AI-assisted tools to improve development efficiency and productivity.