Compiler Backend Engineer

Normal Computing Corporation • Palo Alto, CA

1d

About The Position

Normal Computing is an applied AI company developing foundational hardware and software for the semiconductor industry and AI infrastructure. The company operates across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.

The Compiler Backend Engineer will design and build custom compilation for mapping large-language-model inference onto Normal Computing’s memory-centered, pre-silicon hardware. The role focuses on translating lowered programs into efficient executable code, and on compiler decisions involving scheduling, memory planning, fusion, and dispatch. The engineer will work closely with hardware teams to shape the compiler–hardware abstraction and validate optimizations against simulators and FPGA prototypes, and later against silicon.

Requirements

• Deep experience with compiler optimization or code generation for accelerators or other non-CPU targets, including areas such as scheduling, tiling, fusion, or resource allocation.
• Comfort working close to hardware and reasoning about memory bandwidth and utilization as well as asymptotic complexity.
• Willingness to design compilation approaches from first principles when existing approaches do not fit the hardware.
• A track record of shipping optimizations that improved a measured performance number.
• Comfort building software for evolving hardware, from simulation through bring-up.
• Fluency in Python.
• Familiarity with C, C++, or Rust.

Nice To Haves

• Experience with PyTorch’s compilation stack (TorchDynamo, FX, Inductor, or torch.export) or other ML compilers such as IREE, TVM, or XLA.
• Experience compiling for in-memory, spatial, or other non-von-Neumann compute targets.
• Background in hardware design tools such as logic synthesis or place-and-route.
• Experience building or using cycle-level or performance simulators to guide optimization decisions.
• Contributions to open-source compiler or kernel infrastructure such as PyTorch, Triton, TVM, MLIR, or LLVM.
• Publishing or presenting compiler or performance work at venues such as MLSys, ASPLOS, or CGO.

Responsibilities

• Build code-generation passes that turn lowered programs into executable code for the hardware, developing new compilation approaches where conventional methods do not fit.
• Own scheduling and memory planning across hardware resources, with performance measured by utilization and end-to-end LLM inference latency.
• Own fusion and dispatch decisions for LLM inference to reduce data movement and keep the hardware computing.
• Collaborate with hardware architects on the compiler–hardware abstraction and communicate compiler constraints while hardware design can still change.
• Validate optimizations using measured results from simulators, FPGA prototypes, and eventually silicon.
• Maintain a performance regression suite trusted by the team.
• Take lowered programs from frontend compiler engineers and work with the team to decide which operations are compiler-generated and which use hand-tuned kernels.

What This Job Offers

• Job Type: Full-time
• Education Level: No Education Listed