CMP Process Engineer
About The Position
A CMP (Chemical Mechanical Polishing) Process Engineer is responsible for planarizing wafer surfaces through a combination of chemical reactions and mechanical force. The role aims to produce flat wafer surfaces by controlling these factors so subsequent chip layers can be built with high precision. The engineer controls removal rates, optimizes process conditions and recipes, manages defects and wafer uniformity, monitors consumable life cycles, and evaluates slurries and polishing pads. The role may require working off-hours and/or on a CWW shift schedule according to business needs. All positions at Samsung Austin Semiconductor are full-time and on-site. The role may include access to controlled information or technology under U.S. export control laws; employment may require verification of U.S. Person status or the employer obtaining an export license.
Requirements
- Bachelor's or master's degree in Chemical, Mechanical, Electrical, or Industrial Engineering; Physics; Chemistry; Material Science; or Computer Science.
- At least 5 years of related experience in semiconductor process flows.
- Understanding of dielectric and metal CMP fundamentals, including slurry-pad-conditioning interactions and post-clean steps.
- Proficiency in Statistical Process Control (SPC), Fault Detection and Classification (FDC), and analysis software such as JMP or Spotfire.
- Ability to drive root-cause analysis using methodologies such as FMEA, 8D, and first-principles physics approaches.
- Ability to work off-hour times and/or a CWW shift schedule when required by business needs.
Nice To Haves
- Previous experience in a high-volume semiconductor manufacturing environment; applicable manufacturing experience in other industries may be considered.
- Hands-on familiarity with major industry CMP tools, including AMAT/EBara and their endpoint systems.
- Experience with ellipsometry, SEM, and AFM for thickness and roughness checks.
- Experience identifying killer defects and improving wafer yield.
- Understanding of how CMP affects subsequent Etch/Photo steps and overall yield.
- Ability to run structured Design of Experiments (DOE) for process optimization.
Responsibilities
- Conduct performance evaluations of removal-rate influence factors to maintain consistent wafer thickness skew before and after CMP across the wafer.
- Determine optimal process conditions to improve uniformity and resolve chronic issues such as center-low removal-rate profiles.
- Develop and optimize recipe parameters to improve wafer flatness.
- Manage and improve wafer uniformity and resolve defects such as scratches and particles.
- Monitor consumable usage cycles, including pads and slurry, to ensure they remain within specifications.
- Evaluate slurry and polishing-pad performance to optimize the CMP process.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Life insurance
- 401(k) matching with immediate vesting
- Onsite cafés
- Onsite workout facilities
- Paid maternity leave
- Paid paternity leave
- Paid time off
- Two personal holidays and ten regular holidays
- Wellness incentives
- Eligible full-time employees may receive MBO bonuses based on company, division, and individual performance
- Competitive benefits package
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
