CMP Process Engineer
About The Position
Samsung Austin Semiconductor is seeking a CMP (Chemical Mechanical Polishing) Process Engineer to oversee the wafer planarization step in semiconductor manufacturing. This process combines chemical reactions and mechanical force to create a flat wafer surface, enabling subsequent chip layers to be built with high precision. The engineer controls these factors to achieve consistent wafer thickness and surface quality. The role involves evaluating removal-rate influences, optimizing process conditions and recipes, improving wafer uniformity, and addressing defects such as scratches and particles. The engineer also manages polishing-pad and slurry usage and evaluates consumables to optimize process performance. The position is full-time and on-site at Samsung Austin Semiconductor. Depending on business needs, work during off-hours or on a CWW shift schedule may sometimes be required.
Requirements
- Bachelor's or master's degree in Chemical, Mechanical, Electrical, or Industrial Engineering; Physics; Chemistry; Material Science; or Computer Science.
- At least 5 years of related experience, including semiconductor process flows.
- Understanding of dielectric and metal CMP fundamentals, including slurry-pad-conditioning interactions and post-clean steps.
- Proficiency in Statistical Process Control (SPC), Fault Detection and Classification (FDC), and analysis software such as JMP or Spotfire.
- Ability to drive root-cause analysis using methodologies such as FMEA, 8D, and first-principles physics approaches.
- Flexibility to work off-hours and/or a CWW shift schedule when business needs require.
Nice To Haves
- Previous experience in a high-volume semiconductor manufacturing environment; applicable manufacturing experience in other industries may also be considered.
- Hands-on familiarity with major industry CMP tools such as AMAT and EBara, including their endpoint systems.
- Experience with metrology tools such as Ellipsometry, SEM, and AFM for thickness and roughness checks.
- Experience identifying killer defects and improving wafer yield.
- Understanding of how CMP affects downstream Etch and Photo steps and overall yield.
- Ability to run structured Design of Experiments (DOE) for process optimization.
Responsibilities
- Evaluate factors affecting removal rate to maintain consistent thickness before and after CMP across the wafer.
- Determine optimal process conditions to improve uniformity and resolve chronic issues such as center-low removal-rate profiles.
- Develop and optimize recipe parameters to improve wafer flatness.
- Manage and improve wafer uniformity and resolve defects such as scratches and particles.
- Monitor consumable usage cycles, including pads and slurry, to ensure they remain within specifications.
- Evaluate different slurries and polishing pads to optimize the CMP process.
Benefits
- Medical insurance
- Dental insurance
- Vision insurance
- Life insurance
- 401(k) matching with immediate vesting
- Onsite cafés and workout facilities
- Paid maternity leave
- Paid paternity leave
- Paid time off (PTO)
- Two personal holidays and 10 regular holidays
- Wellness incentives
- Eligible full-time employees may receive MBO bonuses based on company, division, and individual performance
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What This Job Offers
Job Type
Full-time
Career Level
Senior
