Principal Design Engineer CMOS Design Engineer – RF / Mixed-Signal

Northrop Grumman•Manhattan Beach, CA

4d•$114,000 - $171,000•Onsite

About The Position

At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Please be aware that this position is contingent upon capturing program award(s) and obtaining and maintaining associated business and/or customer funding. Seeking a CMOS Design Engineer to design and verify RF and mixed-signal integrated circuits for space payload applications. The engineer will contribute to transistor-level design, simulation, and silicon validation of radiation-tolerant, high-reliability ICs.

Requirements

Bachelor’s degree in Electrical Engineering (or related field) with 5+ years of relevant CMOS design experience; or Master’s degree with 3+ years of relevant CMOS design experience; or PhD with 0–2 years of relevant CMOS design experience.
Hands-on transistor-level CMOS RF and/or mixed-signal IC design experience.
Proficiency with SPICE-based simulation and Cadence (or similar) analog/RF design tools.
Solid understanding of analog/RF fundamentals (noise, linearity, stability, matching, layout‑dependent effects).
Experience with verification methods such as PVT corner and Monte Carlo analysis.
Strong communication skills and ability to collaborate in cross-functional teams.

Nice To Haves

Experience designing ICs for space, radiation-tolerant, or other high-reliability environments.
Background in RF front ends, data converters, PLLs, or clock generation for space payloads.
Experience with lab validation tools (VNAs, spectrum analyzers, oscilloscopes, probe stations).
Familiarity with digital–analog interfaces and mixed-signal verification flows.
Experience with heterogeneous integration approaches
Active security clearance

Responsibilities

Design, simulate, and verify RF / mixed-signal CMOS circuits (e.g., LNAs, mixers, PLLs, ADCs, DACs, bias/reference circuits) for space payloads.
Develop transistor-level architectures and implement designs using industry-standard EDA tools (e.g., Cadence Virtuoso).
Perform PVT corner, Monte Carlo, and noise analyses; support trade studies to meet performance, area, power, and radiation-tolerance goals.
Partner with layout engineers on floorplanning, parasitic optimization, and DRC/LVS closure.
Support top-level integration, design reviews, and technical documentation.
Participate in silicon bring-up, lab characterization, and debug; assist in defining test plans and data analysis.