Principal Engineer, Mixed Signal Logic Design Engineer

Intel•Folsom, CA

1d•Onsite

About The Position

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high-quality integration of the IP block. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related STEM field with 12+ years of relevant experience
Proficiency in System Verilog, including experience with OVM/UVM methodologies.
Demonstrated experience in developing IP or SoC verification environments, writing validation plans, and executing test cases.

Nice To Haves

Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related STEM field with 10+ years of relevant experience, OR PhD in a related STEM field with 8 years of experience.
3+ years of experience with DFI/DDR/LPDDR Protocols.
Experience in DDR Phy verification or Memory Controller verification.
Strong problem-solving skills and a proactive approach to tackling complex technical challenges.
Ability to work collaboratively across multidisciplinary teams to achieve technical goals.

Responsibilities

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed signal and/or highspeed IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs.
Participates in the definition of architecture and microarchitecture features of the block being designed.
Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.
Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Supports SoC customers to ensure high-quality integration of the IP block.
As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry.
Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values.
Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.