Mixed Signal Logic Design Engineer

Intel•Hillsboro, OR

1d•$141,910 - $200,340•Onsite

About The Position

As a Mixed Signal Logic Design Engineer, you will play a pivotal role in shaping the future of high-speed and mixed signal IP designs at Intel. Your contributions will directly impact the development of cutting-edge technologies that enable the integration of functional units, IP blocks, and subsystems into full chip designs. This position is at the forefront of innovation, requiring collaboration with cross-functional teams to define architecture and microarchitecture features, optimize performance, and ensure design integrity. Your work will drive Intel's success in achieving power, performance, and area goals, empowering our customers with industry-leading solutions.

Requirements

BS degree in Electrical Engineering or Computer Engineering or similar field of study with 4+ years relevant experience -OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 3+ years relevant experience.
3+ years of experience: With standard digital design concepts such as FSM design techniques
With SystemVerilog
With computer architecture, analog design, ADC/DAC designs, communications theory, and/or microarchitecture design concepts
With multiple clock-domain design

Nice To Haves

BS degree in Electrical Engineering or Computer Engineering or similar field of study with 7+ years relevant experience OR- MS degree in Electrical Engineering or Computer Engineering or similar field of study with 5+ years relevant experience.
Able to work highly independently, guide other junior team members and make contributions that increase the productivity of the entire design team
Excellent communication and interpersonal skills
Experience with both logic and analog circuits as well as with analog behavioral modeling
Knowledge of mixed-signal validation, signal, and systems analysis
Knowledge of High-Speed I/O protocol stacks (UCIe, PCIe, USB, etc.)
Experience with scripting languages e.g. Perl, bash/csh and Python is highly desirable
Experience mentoring junior designers to deliver quality designs
Experience using RTL quality tools such as linting and CDC analysis and supporting team adoption and usage
Experience with low-power design, power gating, and multiple power-domain design
Experience with writing, testing, packaging, and releasing firmware
Experience writing, testing, and supporting front-end automation and packaging flows
Experience using AI tools as a productivity booster in all aspects of the IP design process
Strong analytical debugging skills, with a creative approach to problem-solving

Responsibilities

Develop architecture and microarchitecture specifications for the logic components and contribute to the overall system architecture decisions
Implement specifications/designs in RTL and coordinate the work of other junior designers to deliver high-quality, complex logic blocks
Develop behavioral models that represent analog and mixed-signal circuit blocks using SystemVerilog
Run simulations and debug using logic, mixed-signal validation, and AMS simulation tools
Ensure high-quality designs by using industry standard tools such as linting and CDC analysis
Support the physical design team in implementing your designs, including synthesis and timing closure
Work with the pre-silicon validation/verification team to develop test plans and verification collateral
Work with post-silicon validation teams to resolve post-silicon issues