Chip Simulation Lead

Etched • San Jose, CA

4d • Onsite

About The Position

Etched is building hardware for frontier intelligence, co-designing chips, racks, software, and manufacturing to deliver throughput and latency across prefill and decode workloads. Its first products focus on inference.

The Lead Chip Simulation Engineer will drive the technical direction and development of custom AI accelerator simulation infrastructure. The simulation team builds hardware models that enable software development, debugging, and hardware-software co-design before silicon is available. This highly technical leadership role guides engineers developing a bit-accurate, cycle-aware chip simulator; reviews designs and code; and ensures simulation infrastructure is accurate, performant, scalable, and maintainable. The role works closely with hardware architects, firmware, kernel, and software teams to identify technical challenges, set priorities, and enable early development of the full software stack. The lead will mentor engineers and remain hands-on with critical implementations, debugging, and architectural prototyping.

Etched is a fully in-person team based in San Jose (Santana Row). Technical staff are expected to contribute to both engineering and research and work across disciplines as needed.

Requirements

• Deep expertise in C/C++ and low-level systems software development.
• Experience leading complex technical projects and guiding engineers through design, implementation, and code reviews.
• Strong understanding of computer architecture, hardware-software interfaces, and systems programming.
• Experience building or developing hardware simulators, architectural models, or other complex systems software.
• Ability to make architectural decisions, evaluate technical tradeoffs, and maintain high engineering standards.
• Strong debugging and problem-solving skills across hardware and software boundaries.
• Experience mentoring engineers and collaborating across technical disciplines.
• Track record of owning complex software systems from architecture through delivery.

Nice To Haves

• Experience developing hardware or system simulators using SystemC, gem5, QEMU, or custom simulation frameworks.
• Experience with cycle-accurate, cycle-aware, or bit-accurate hardware modeling.
• Experience with custom AI accelerators, GPUs, CPUs, or SoC architectures.
• Experience in firmware, kernel, and driver development, including Linux or FreeRTOS.
• Experience with hardware verification and validation methodologies.
• Experience with multithreaded and multiprocessing simulation frameworks.
• Experience with simulation performance profiling and optimization.
• Experience with Python-based testing infrastructure, Bazel, and Git.
• Experience leading small technical teams or owning simulation infrastructure in a semiconductor or accelerator startup.

Responsibilities

• Provide technical leadership for the chip simulation team, guiding engineers through architecture, implementation, debugging, and performance optimization.
• Own the technical direction of simulation infrastructure, ensuring accuracy, scalability, performance, and maintainability.
• Lead design and code reviews, establish engineering best practices, and maintain a high bar for code quality.
• Mentor and support engineers as they navigate complex technical challenges.
• Drive hardware-software co-design with hardware architects and software teams to influence architecture and enable pre-silicon development.
• Oversee simulator integration, including simulated hardware modules, QEMU-based host integration, and multi-chip simulation.
• Guide validation and testing strategies to ensure simulation correctness and alignment with hardware specifications.
• Contribute hands-on to critical implementations, debugging, and architectural prototyping when needed.
• Lead development of simulation models for the custom AI accelerator and guide the development and validation of bit-accurate and cycle-aware on-chip module models.
• Review and drive integration of simulated chips with QEMU hosts for kernel driver development and host software testing.
• Define multi-chip simulation architecture to validate scale-out and scale-up approaches.
• Establish code review, testing, and debugging practices that improve simulator accuracy and engineering velocity.
• Partner with hardware architects and software engineering leads to resolve complex pre-silicon issues and guide technical decisions.

Benefits

• Medical, dental, and vision packages with generous premium coverage.
• $500 per month credit for waiving medical benefits.
• Housing subsidy of $2,500 per month for those living within walking distance of the office.
• Relocation support for those moving to San Jose (Santana Row).
• Wellness benefits covering fitness, mental health, and more.
• Daily lunch and dinner in the office.
• Unlimited compute budget subject to ROI justification.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed