Chief Engineer & Architect, MRAM

Western Digital•San Jose, CA

14h

About The Position

The Chief Engineer & Architect, MRAM is the most senior technical individual contributor in memory design at WD. The role owns end-to-end product architecture from concept through silicon qualification, makes power, performance, and area trade-offs that shape product competitiveness, and serves as the final technical authority across design, process, and product engineering. The position defines memory subsystem architecture—including array, periphery, I/O, redundancy, test, and reliability—and translates product requirements into design specifications. It drives floorplan and physical architecture, including array efficiency, periphery partitioning, power delivery, and die-level signal integrity. The role owns a multi-generation roadmap covering node migration, density, and performance scaling; decides cross-functional trade-offs spanning process integration, circuits, DFT, packaging, and controller/firmware interfaces; and directs design methodology and EDA/CAD strategy, including tools, flows, vendors, and licenses. It also mentors senior and principal engineers and represents the architecture to executives, customers, foundry partners, and standards bodies.

Requirements

MS or PhD in EE, CE, or a related field.
15+ years in memory or mixed-signal IC development, including 5+ years as an architect or chief engineer.
Owned at least two memory products from architecture through production silicon.
Deep advanced CMOS FinFET expertise, including layout, variability, reliability, and DFM.
Broad memory architecture knowledge across DRAM, NAND/NOR, SRAM, and emerging NVM, with depth in one area.
Experience with modern Cadence/Synopsys custom and digital flows through full-chip sign-off.
Owned EDA/CAD strategy.
Led multi-site programs through influence.

Nice To Haves

Embedded memory IP integration into SoCs and memory-controller co-design.
Foundry engagement on PDKs, test chips, and DTCO.
Emerging NVM architecture experience.
JEDEC involvement, patents, or publications.

Responsibilities

Own end-to-end product architecture from concept through silicon qualification.
Arbitrate power, performance, and area trade-offs that determine product competitiveness.
Serve as the final technical authority across design, process, and product engineering.
Define memory subsystem architecture, including array, periphery, I/O, redundancy, test, and reliability, and translate product requirements into a design specification.
Drive floorplan and physical architecture, including array efficiency, periphery partitioning, power delivery, and die-level signal integrity.
Own the multi-generation roadmap, including node migration and density and performance scaling.
Decide cross-functional trade-offs across process integration, circuits, DFT, packaging, and controller/firmware interfaces.
Own design methodology and EDA/CAD strategy, including tools, flows, vendors, and licenses.
Mentor senior and principal engineers through architecture and design reviews.
Represent the architecture to executives, customers, foundry partners, and standards bodies.

Benefits

Paid vacation time
Paid sick leave
Medical insurance
Dental insurance
Vision insurance
Life insurance
Accident insurance
Disability insurance
Tax-advantaged flexible spending and health savings accounts
Employee assistance program
Supplemental life and AD&D
Legal plan
Pet insurance
Critical illness, accident, and hospital indemnity programs
Tuition reimbursement
Transit benefits
Applause Program
Employee stock purchase plan
WD Savings 401(k) Plan
Potential eligibility for bonuses under the Short Term Incentive Plan or Sales Incentive Plan
Potential eligibility for the annual Long-Term Incentive program, consisting of restricted stock units or cash equivalents
Restricted stock unit awards for eligible new hires