Chief Engineer & Architect, MRAM
About The Position
WD is seeking its most senior technical individual contributor in memory design. The role owns end-to-end product architecture from concept through silicon qualification, makes power, performance, and area trade-offs that determine product competitiveness, and serves as the final technical authority across design, process, and product engineering. The position defines memory subsystem architecture and product design specifications; drives floorplan and physical architecture; and owns a multi-generation roadmap covering node migration, density, and performance scaling. It also makes cross-functional decisions across process integration, circuits, DFT, packaging, and controller and firmware interfaces; sets design methodology and EDA/CAD strategy; mentors senior and principal engineers; and represents architecture to executives, customers, foundry partners, and standards bodies.
Requirements
- MS or PhD in EE, CE, or a related field.
- 15+ years in memory or mixed-signal IC development, including 5+ years as an architect or chief engineer.
- Ownership of at least two memory products from architecture through production silicon.
- Deep advanced CMOS FinFET expertise, including layout, variability, reliability, and DFM.
- Breadth in memory architecture (DRAM, NAND/NOR, SRAM, and emerging NVM), with depth in one area.
- Experience with modern Cadence/Synopsys custom and digital flows through full-chip sign-off.
- Experience owning EDA/CAD strategy and leading multi-site programs through influence.
Nice To Haves
- Embedded memory IP integration into SoCs and memory-controller co-design.
- Foundry engagement on PDKs, test chips, and DTCO.
- Emerging NVM architecture experience; JEDEC involvement, patents, or publications.
Responsibilities
- Own end-to-end product architecture from concept through silicon qualification.
- Arbitrate power, performance, and area trade-offs that set product competitiveness.
- Serve as the final technical authority across design, process, and product engineering.
- Define memory subsystem architecture, including array, periphery, I/O, redundancy, test, and reliability, and translate product requirements into a design specification.
- Drive floorplan and physical architecture, including array efficiency, periphery partitioning, power delivery, and die-level signal integrity.
- Own the multi-generation roadmap for node migration, density scaling, and performance scaling.
- Decide cross-functional trade-offs across process integration, circuits, DFT, packaging, and controller/firmware interfaces.
- Own design methodology and EDA/CAD strategy, including tools, flows, vendors, and licenses.
- Mentor senior and principal engineers through architecture and design reviews.
- Represent the architecture to executives, customers, foundry partners, and standards bodies.
Benefits
- Paid vacation time and paid sick leave.
- Medical, dental, and vision insurance.
- Life, accident, and disability insurance.
- Tax-advantaged flexible spending and health savings accounts.
- Employee assistance program.
- Voluntary benefits, including supplemental life and AD&D, legal plan, pet insurance, critical illness, accident, and hospital indemnity coverage.
- Tuition reimbursement.
- Transit benefits.
- Applause Program.
- Employee stock purchase plan.
- WD Savings 401(k) Plan.
- May be eligible for bonuses under the Short Term Incentive Plan or Sales Incentive Plan.
- May be eligible for the annual Long-Term Incentive program, which may include restricted stock units or cash equivalents.
- Restricted stock unit awards may be available to eligible new hires.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Principal
