Camera Subsystem Integration Lead

Qualcomm•San Diego, CA
•$216,600 - $325,000

About The Position

Qualcomm Technologies, Inc.'s Multimedia Camera HW team seeks an experienced ASIC Design and Subsystem Integration Engineer to lead the integration of Camera and Image Processing subsystems into next-generation SoCs. The senior team member provides technical leadership for Camera subsystem integration and works closely with architecture, design, design verification (DV), physical design, software, power, and SoC teams. The role owns subsystem-level RTL integration across multiple Camera and Image Processing IPs, including clocks, resets, power domains, registers and address maps, interrupts, buses and interconnects, and configuration paths. It drives integration of new IPs, features, and SoC-facing interfaces; RTL baselines and release readiness; RTL quality checks and implementation tradeoff evaluation; and subsystem-level verification planning and complex cross-IP debugging. The lead also identifies risks, improves integration methodology and automation, and provides technical guidance and mentorship. The environment is fast-paced and involves significant cross-functional interaction.

Requirements

  • 10+ years of industry experience in ASIC/SoC design and integration.
  • Experience in Verilog/SystemVerilog RTL design and debugging.
  • Experience with complex ASIC/SoC subsystem integration.
  • Experience with design verification and subsystem-level verification methodologies.
  • Knowledge of SoC bus/interconnect protocols such as AHB and AXI.
  • Experience with clock, reset, interrupt, register, and power-domain integration.
  • Experience with RTL quality methodologies, including lint, CDC/RDC, synthesis, timing analysis, and low-power checks.
  • Experience working across Design, DV, Architecture, Physical Design, Software, and SoC teams.
  • Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field and 8+ years of relevant work experience; or a master's degree in one of these fields and 7+ years; or a PhD in one of these fields and 6+ years.

Nice To Haves

  • Experience with Camera, Image Processing, Video, Multimedia, Graphics, or DSP hardware.
  • Experience with ASIC implementation and integration of Camera/Image Processing IP.
  • Understanding of high-bandwidth data paths, memory systems, NoC/interconnects, and performance optimization.
  • Experience with low-power methodologies and UPF-based flows.
  • Experience with Python, Perl, Tcl, or similar scripting languages for automation.
  • Experience taking complex ASIC subsystems from architecture and RTL through verification, SoC integration, tapeout, and silicon bring-up.

Responsibilities

  • Own and drive Camera subsystem-level RTL integration across multiple Camera and Image Processing IPs.
  • Collaborate with hardware and system architects to define subsystem architecture, interfaces, and integration requirements.
  • Lead integration of new IPs, features, and SoC-facing interfaces.
  • Own top-level integration of clocks, resets, power domains, registers and address maps, interrupts, buses and interconnects, and configuration paths.
  • Drive RTL baseline, integration, and release readiness for key project milestones.
  • Run and review RTL quality checks, including lint, CDC/RDC, low-power checks, connectivity checks, synthesis, and timing analysis.
  • Evaluate performance, power, area, scalability, and implementation tradeoffs.
  • Partner with DV teams to define subsystem-level verification requirements and integration test scenarios.
  • Lead debug of complex issues spanning multiple IPs and subsystem/SoC boundaries.
  • Identify integration risks early and drive cross-functional technical issues to closure.
  • Drive integration methodology and automation improvements to improve quality and execution efficiency.
  • Provide technical guidance and mentorship to engineers across the Camera HW team.

Benefits

  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for the annual bonus).
  • Competitive benefits package designed to support employees at work, at home, and at play.
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