Bench Test Engineer

Qualcomm•San Diego, CA

2d•$94,200 - $141,200

About The Position

The Post Silicon Engineering group that develops test solutions for highly integrated SOCs (System on Chip) is seeking engineers who excel in silicon debug, high-speed interface analysis, and data-driven optimization of complex mixed signal systems and who are motivated to drive issues to closure across cross‑functional teams. If you are passionate about delivering quality work products, seek to continually learn about new products as well as essential knowledge of industry trends, competitor products, and advances in various engineering fields from publicly available information and assist in conducting specialized analyses (e.g., feasibility studies, signal integrity, teardown analyses) – apply here!

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Nice To Haves

1-3+ years of experience in related areas. (fresh graduates welcome to apply)
Experience with Python/C# for test automation is required
Master's Degree in Electrical/Computer Engineering or related field.
Strong understanding of VLSI technologies, CMOS analog and digital integrated circuits, mixed-signal and semiconductor physics.
Knowledge of High-Speed test and characterization including eye diagram characteristics, differential signals, jitter analysis, signal integrity etc. is preferred.
Familiarity with DDR 2/3/4/5, LPDDR 2/3/4/5 protocol, interface, IO receiver/transmitter, timing diagrams and device specifications is a plus.
Hands-on experience with lab equipment such as Oscilloscopes, TDRs/VNAs, J-BERT etc. and power measurement tools is preferred.
Familiarity with Board Design concepts (Schematic reviews, Layout best practices etc.) is a plus.
Strong ASIC device level characterization skills. System level knowledge is a plus.
Knowledge in test automation development/scripting/debugging is a plus.
Strong verbal and written communications skills as well as good organization and documentation skills.
Strong problem solving & debugging skills. Ability to work independently and with good initiative to overcome technical challenges.
Strong Interpersonal and teamwork skills with proven ability to work effectively in a fast-paced multi-disciplinary environment.
Ability to document characterization results, debug findings, methodology updates, and design recommendations with clarity and technical rigor.
Able to work independently and with good initiative to overcome technical challenges. Meeting project deadlines and characterization (char) milestones would be required.
Strong verbal and written communications skills. Effective communication within and outside the team is essential. Clear, data-driven analysis and preparing high quality reports, and presenting them effectively to internal stakeholders across teams is required. Able to organize effectively and document work thoroughly while working with local and remote team including debug findings, methodology updates, and design recommendations with clarity and technical rigor.

Responsibilities

Define and execute the development of Test methodologies and characterization of leading-edge LP-DDR & PC-DDR Subsystem components (DRAM, DRAM Controller, Mixed Signal PHY IP, IO circuits and termination network, Clocking architecture, Delay circuits, Power Distribution Network) as well as other proprietary interfaces.
Develop and execute characterization plans for High Speed IPs to optimize design parameters and validate electrical compliance, driving corresponding first silicon bring-up & debug to qualify designs fabricated at external foundries.
Perform parametric analysis of silicon behavior over various operating process, voltage and temperature conditions and configurations, and driving root‑cause failure analysis to closure for design, test, or system‑level issues.
Developing and automate test scripts, measurement procedures, and data processing flows to accelerate silicon evaluation, improve turnaround time, and enable data‑driven decision‑making during bring‑up and characterization phases.
The engineer will contribute to guard‑banding strategies and characterization sign‑off to support downstream manufacturing readiness.
Assist in HW design and debug power integrity (PI) and signal integrity (SI) issues related to package and board design.
Work closely with cross-functional teams such as IC Design, Systems Engineering for chip/circuit bring -up, debug and feature enablement. The role also requires close collaboration with Customer Engineering and Hardware Applications teams to resolve customer issues/RMA debug in a time-critical environment including providing clear debug analysis, technical recommendations, and design feedback.