ASIC Technical Lead - DFT - Silicon One

Cisco • San Jose, CA

4d • $183,800 - $303,100

About The Position

You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Requirements

• Bachelor's or a Master’s Degree in Electrical or Computer Engineering required with at least 8 years of experience.
• Prior experience with Jtag protocols ( p1500, p1500, p1687) , Scan insertion and BIST architectures, including memory BIST and boundary scan.
• Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, test static timing analysis constraints development and timing closure.
• Prior experience working with Gate level simulation, including timing based simulations.
• Post-silicon validation and debug experience; Ability to work with ATE engineers on pattern translation and validation.
• Scripting skills: Tcl, Python/Perl.

Nice To Haves

• Verilog design experience – developing custom DFT logic & IP integration; familiarity with functional verification
• DFT CAD development – Test Architecture, Methodology and Infrastructure

Responsibilities

• Manages the definition, architecture and design of high performance ASICs
• Owns applications or multiple complex functional areas
• Oversees reusable code and its applications
• Creates re-usable code that promotes efficiencies in new ways
• Defines verification strategies
• Coordinates with appropriate stakeholders to integrate into PD and DV flows
• Owns infrastructure and testing environmens
• Leads and designs the building blocks of multiple channels
• Applies and drives the design methodology from conception to production
• Influences and collaborates with teams to ensure specifications and requirements are met
• Leads technical expertise of a physical design function
• Interfaces with vendors and design leads on full chip timing closure, PI, and PV
• Owns the full electrical planning and specifications of electrical interfaces
• Develops multiple solutions, first test vehicles and performs verification and validation

Benefits

• medical, dental and vision insurance
• a 401(k) plan with a Cisco matching contribution
• paid parental leave
• short and long-term disability coverage
• basic life insurance
• grants of Cisco restricted stock units
• 10 paid holidays per full calendar year
• 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday
• paid year-end holiday shutdown
• 4 paid days off for personal wellness
• 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
• flexible vacation time off program
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• annual bonuses

What This Job Offers

• Job Type: Full-time
• Career Level: Senior