Senior ASIC Timing Engineer, DFT
About The Position
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence. Our team has some of the most forward-thinking and hardworking people in the world. We are now looking for a motivated DFT-Timing Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today!
Requirements
- BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years’ experience or MS (or equivalent experience) with 2+ years’ experience.
- Hands-on experience in Static Timing Analysis (STA) and driving timing convergence at full-chip/sub-chip level in advanced technology nodes.
- Expertise in analysis and fixing of timing paths through ECOs.
- Expertise in developing timing constraints.
- In-depth knowledge of industry standard timing convergence tools.
Nice To Haves
- Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan, iJTAG, etc.
- Background in domain specific STA and timing convergence, such as Serdes, Processor, IO, SMVA, etc.
- Experience in methodology and/or workflow development.
Responsibilities
- Drive timing analysis and closure for DFT logic on all Nvidia chips (GPUs/CPUs/DPUs/LPUs/SoCs) at all hierarchical levels (block/cluster/full-chip).
- Work with PD, DFX, Clocks and other teams to come up with timing closure strategy, develop timing constraints for custom DFT designs, drive timing and power convergence, and implement ECOs.
- Continuously improve workflows and designs by introducing more automation, resilience, and standardization.
Benefits
- equity
- benefits
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What This Job Offers
Job Type
Full-time
Career Level
Senior
