Senior DfT Engineer
About The Position
As a DfT engineer, you will join a highly experienced team. Your key responsibilities will be to closely collaborate with various leads and engineers to identify the superset of requirements for Testability of the chip (Functional mode, Debug mode, ATPG). You will gain a deep understanding of existing and innovative ways to insert DfT for complex analog and mixed-signal IPs, standard Macros (RAM, ROM, NVM, ADC, DAC) and complex digital logic. You will be responsible for high-quality RTL design using Verilog and System-Verilog, defining the Verification Plan for implemented features, and writing tests, debugging, and ensuring their passing at the Chiptop level DV environment. This includes scan insertion, optimization, length balancing, P&R-aware rerouting of chains, Test-Point insertion, ATPG patterns generation, simulation, and debug. You will also support Test Engineers during pattern debug on new silicon and customer returns, participate in Design & Test Review meetings, and support the team for DfT. Additionally, you will generate comprehensive DfT Architecture & Design documentation and maintain it, troubleshoot and resolve issues related to DfT throughout the development lifecycle, and stay updated with the latest industry trends, tools, and methodologies in DfT design.
Requirements
- Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL coding, DfT, Computer Architecture, Digital Verification.
- Minimum 3 years of experience in similar role of DfT, Digital Design & Architecture.
- Seeking 3-8 years total experience for this role
- Excellent on problem-solving, teamwork, planning, organizing, attention to detail and communication skills.
Responsibilities
- Closely collaborate with Product Definer, Analog Design Lead, Digital Design Lead, Test Lead, Product Engineer, Quality Engineer, Validation Engineer – to identify the superset of requirements for Testability of the chip (Functional mode, Debug mode, ATPG).
- Gain deep understanding on existing and innovative ways to insert DfT for complex analog and mixed-signal IPs, standard Macros (RAM, ROM, NVM, ADC, DAC) and complex digital logic.
- High-quality of RTL design using Verilog and System-Verilog
- Define Verification Plan for the implemented features and write tests, debug and get those passing at Chiptop level DV environment
- Scan insertion, optimization, length balancing, P&R-aware rerouting of chains, Test-Point insertion, ATPG patterns generation, simulation and debug
- Support Test Engineers during debug of patterns on new silicon, and on customer returns
- Participate in Design & Test Review meetings and support the team for DfT
- Generate comprehensive DfT Architecture & Design documentation and maintain it to match later updates
- Troubleshoot and resolve issues related to DfT throughout the development lifecycle
- Stay updated with the latest industry trends, tools, and methodologies in DfT design
Benefits
- online and offline learning opportunities to help you develop some of your core and professional skills.
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What This Job Offers
Job Type
Full-time
Career Level
Senior
