ASIC Power Engineer, ML Accelerators

Google•Sunnyvale, CA
•$163,000 - $236,000

About The Position

As an ASIC Power Engineer on Google’s TPU power design team, you will help improve the power efficiency of Tensor Processing Units used to accelerate computation in data centers. You will drive power efficiency from building power models through proposing and deploying power optimization techniques, drawing on a background in chip power modeling and optimization and understanding of system-level power considerations and tradeoffs. You will contribute to the design, architecture, documentation, and implementation of the next generation of data center accelerators. The role is part of Google’s AI and Infrastructure team, which develops AI and infrastructure capabilities at scale, including custom silicon and TPUs.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in silicon design or architecture, such as logic design, power architecture, performance, or SoC design.
  • Experience with power design, power modeling, power architecture, or power reduction methodologies and techniques.

Nice To Haves

  • Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
  • Experience defining and implementing chip-wide power management architectures and designs.
  • Experience in power modeling, measurement, and correlation across pre- and post-silicon phases.
  • Understanding of modern power and thermal management techniques at both silicon and system levels, including DVFS, turboing, thermal management, and system-level tradeoffs.
  • Ability to solve open-ended power and performance problems under ambiguity.

Responsibilities

  • Contribute to design power modeling and drive convergence to power goals.
  • Investigate, specify, and deploy architectural and microarchitectural power optimization techniques.
  • Define best practices and methodologies to achieve low-power designs.
  • Collaborate with cross-functional software and system teams to create novel power management architectures to meet power goals.

Benefits

  • 15% bonus target
  • Equity
  • Benefits (details are available through Google’s benefits information link).
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