As an ASIC Power Engineer on Google’s TPU power design team, you will help improve the power efficiency of Tensor Processing Units used to accelerate computation in data centers. You will drive power efficiency from building power models through proposing and deploying power optimization techniques, drawing on a background in chip power modeling and optimization and understanding of system-level power considerations and tradeoffs. You will contribute to the design, architecture, documentation, and implementation of the next generation of data center accelerators. The role is part of Google’s AI and Infrastructure team, which develops AI and infrastructure capabilities at scale, including custom silicon and TPUs.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
Job Type
Full-time
Career Level
Senior