ASIC & FPGA Design Engineer Sr

Lockheed Martin•Orlando, FL

18h•Hybrid

About The Position

You will be the Senior ASIC & FPGA Design Engineer for the Command Launch Assembly (CLA) FPGA team within Missiles & Fire Control (MFC). Our team delivers the digital heart beat that powers the Next Generation Short Range Interceptor (NGSRI), turning system level performance and safety goals into reliable, production ready FPGA hardware for the United States and allied forces. As the senior ASIC & FPGA designer you will own the full lifecycle of the CLA FPGA—from high level architecture through release ready documentation—while mentoring junior talent and partnering with a broad set of cross functional experts.

Requirements

Bachelor of Science degree in Electrical Engineering or a closely related STEM field from an accredited university; Master’s degree preferred
Minimum 3 years of professional experience with FPGA design and simulation verification or a related discipline
Proficiency in HDL programming with VHDL, Verilog, and/or SystemVerilog
Experience with Xilinx/AMD toolsets (Vivado, Vitis, Vitis HLS) and UltraScale design methodology
Experience with FPGA simulation tools such as Synopsys VCS
Strong understanding of digital design principles, including timing analysis, clock domain crossing, and signal integrity
Experience with high-speed interfaces such as AXI, Ethernet, TCP/IP, PCIe, and serial protocols
Practical laboratory debug experience with high-speed oscilloscopes, spectrum analyzers, and signal generators
Familiarity with Synopsys EDA tools
Must be a US Citizen; must possess or be able to obtain a DoD Secret clearance

Nice To Haves

LM/MFC design experience and missile program experience
Experience with SystemVerilog, Verilog, C/C++, MATLAB/Simulink; Synopsys Synplify, Synopsys VCS, NCSim, ChipScope tool sets
Experience with Xilinx/AMD and MicroSemi/Microchip part families, internal FPGA fabric and IP
Experience implementing NSA algorithms (e.g., AES, counter mode)
Experience managing configuration control (GitLab preferred)
Experience with Vivado and Vitis FPGA toolsets
Experience with UVM and Simulink/HDL Coder integration
Comfortable using digital oscilloscopes, spectrum analyzers, power meters, signal generators, and other test equipment
Experience with troubleshooting and debugging at board level, including FPGA validation
Experience in full ASIC/FPGA lifecycle (architecture, design, simulation, verification, validation, integration & test)
Strong communication, collaboration, and presentation abilities
Controls and digital loop-closure application knowledge
Networking proficiency with Ethernet switches, routers, firewalls, and debugging tools (tcpdump, Wireshark)
Active DoD Secret or Top Secret clearance

Responsibilities

Defining FPGA architecture and drafting design specifications; writing clean RTL in VHDL/Verilog/SystemVerilog that satisfies performance, power, and reliability targets.
Developing synthesis, place and route, and timing closure strategies to guarantee deterministic operation on the chosen FPGA families.
Building comprehensive test plans, simulation models, and verification environments (UVM, SystemC, Python based testbenches) to prove functional correctness and timing margins.
Leading hardware in the loop (HIL) tests, board level debugging, and subsystem integration activities.
Translating system level performance, safety, and reliability requirements into detailed FPGA architectures and resource utilization studies.
Conducting timing analysis, power budgeting, and device selection optimization.
Managing configuration control with GitLab (or equivalent), maintaining version controlled repositories, and ensuring full traceability of all design artifacts.
Producing complete design packages—specifications, test plans, verification reports, and release documentation—compliant with aerospace and Lockheed Martin command media standards.
Collaborating with systems, software, hardware, mechanical, test, manufacturing, and quality teams to keep the program on schedule and within performance envelopes.
Mentoring junior engineers, championing best practice FPGA development, verification, and configuration management processes.