ASIC Floorplan Design Engineer - New College Grad 2026

NVIDIA•Santa Clara, CA

9d•$116,000 - $218,500

About The Position

NVIDIA is seeking an ASIC Floorplan Engineer to design and implement SoCs and GPUs. The role contributes to the design and development of next-generation GPUs and SoCs, with potential impact across consumer graphics, self-driving cars, and artificial intelligence products. Working with architects, design leads, physical design leads, and package leads, the engineer develops and optimizes floorplans during early chip development. The position also involves reviewing area, addressing timing and routing congestion, and developing or improving tools and infrastructure to optimize chip area and execution speed.

Requirements

Master’s degree in Electrical Engineering, Computer Science, or Computer Engineering, or equivalent experience.
Deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
Experience with Verilog, SystemVerilog, or a similar hardware verification language (HVL).
Experience with CAD and physical design methodologies, including flow and tool development, chip floorplanning, power and clock distribution, packaging, place and route (P&R), and timing closure.
Strong communication and interpersonal skills, and the ability and desire to work effectively as a teammate.
Experience with Python, Perl, and C/C++ programming languages.

Nice To Haves

Experience driving the development of large-scale ASIC floorplans.

Responsibilities

Develop and optimize floorplans during early chip development in collaboration with architects, design leads, physical design leads, and package leads.
Drive the area review process and work with the ASIC design team to identify opportunities to improve area, interconnect, and floorplan.
Address timing and routing congestion with physical design and ASIC design teams by influencing early design and physical implementation decisions.
Build tools and improve existing infrastructure to optimize chip area and speed of execution.