ASIC Failure Analysis Engineer (Hybrid)

Cisco•San Jose, CA

2d•Hybrid

About The Position

The ASIC Failure Analysis Engineer is part of Cisco’s Quality and Reliability group and performs failure analysis of ASIC products. The role focuses on root cause analysis of silicon product reliability-test and field failures, interpreting results from semiconductor failure-analysis techniques, and providing clear guidance on failure causes and corrective actions. The position involves close collaboration with Product Test Engineering, Design Engineering, Quality Engineering, Assembly Engineering, and Foundry Engineering. The engineer develops and implements systematic failure-analysis processes, coordinates analysis logistics and instructions, documents findings for management, serves as a technical resource, and maintains relationships with failure-analysis service and equipment vendors. The role also supports fault isolation, identification, and characterization for yield and reliability issues in emerging technologies. This is a hybrid position with approximately three or more days per week in the San Jose, California office.

Requirements

Bachelor’s degree in Electrical/Electronics Engineering or a related field.
At least 8 years of experience in semiconductor failure analysis.
Experience writing and executing failure-analysis plans and interpreting results from cross section, X-ray, CSAM, TDR, FIB, SEM, TEM, IR/EMMI, and OBIRCH techniques.
Validated ability to specify hardware and implement setup for dynamic failure analysis using SIL (Solid Immersion Lens) and LSM (Laser Scanning Microscopy).
Experience using ATE, Scan/ATPG, and MBIST fault-isolation techniques to identify, isolate, and characterize device-level faults.
Strong communication and organizational skills, including the ability to collaborate with teams, customers, and vendors.

Nice To Haves

Master’s degree.
Knowledge of semiconductor technology and processes, including fabrication, assembly, and advanced packaging.
Understanding of transistor function, basic electronics, semiconductor device physics, and behavior under various operating conditions.
Proficiency in ATE-docked dynamic fault isolation using LVP, LVI/SMI, LADA, and TIVA techniques.
Knowledge of JEDEC IC qualification tests and requirements.
Applied experience driving physical failure analysis with suppliers.

Responsibilities

Conduct root cause failure analysis of silicon product reliability-test and field failures, and propose corrective actions.
Develop and implement standard failure-analysis processes using failure-analysis equipment.
Coordinate logistics and instructions to direct the failure-analysis process and carry out the function systematically.
Document and report failure-analysis results to management.
Serve as a technical resource for failure-analysis questions.
Develop and maintain relationships with failure-analysis service and equipment vendors.
Work with product, test, and design engineering groups to identify and characterize faults on emerging technologies.
Provide fault isolation, identification, and characterization for yield and reliability failures.

Benefits

Medical, dental, and vision insurance, subject to plan eligibility rules.
401(k) plan with Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Paid holidays and a floating holiday for non-exempt employees.
Birthday day off, paid year-end holiday shutdown, and personal wellness days.
Paid vacation or flexible vacation time off, depending on employee classification.
Sick time off, with carryover subject to the stated limits.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonus eligibility for non-sales roles, subject to Cisco policies.
Potential grants of Cisco restricted stock units, subject to eligibility and vesting terms.