ASIC Engineering Technical Leader

Capgemini • San Jose, CA

5d • Onsite

About The Position

We are seeking an ASIC Engineering Technical Leader with strong expertise in Design‑for‑Test (DFT) for next‑gen optical communication ASICs. Responsibilities include DFT architecture implementation, scan insertion, ATPG pattern generation, silicon debug, integration/verification of DFT fabrics, gate‑level simulations, and automation using Python/Tcl/C++ .

Requirements

• BS + 8 yrs / MS + 6 yrs / PhD + 3 yrs experience
• Proven background in ASICs, DFT setup, scan insertion, and validation
• Hands-on with Siemens Tessent, ATPG, Memory/Logic BIST
• Strong scripting (Python/Tcl/C++) and RTL debugging skills

Nice To Haves

• 10+ yrs ASIC/DFT experience
• SSN expertise
• ATE tester exposure
• Verilog/SystemVerilog integration
• Advanced silicon process knowledge

Responsibilities

• DFT architecture implementation
• Scan insertion
• ATPG pattern generation
• Silicon debug
• Integration/verification of DFT fabrics
• Gate-level simulations
• Automation using Python/Tcl/C++

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed