ASIC Engineering Technical Leader- DFT

Cisco•San Jose, CA

11d•$210,600 - $305,100•Onsite

About The Position

The applicant will be in the Silicon One development organization as an ASIC Technical Lead in San Jose with a primary focus on Design-for-Test. They will work with Front-end RTL teams and backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a member of this team, they will also be involved in crafting groundbreaking next generation networking chips. They will help lead to drive the DFT and quality process through the entire Implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Requirements

Bachelor's or a Master's Degree in Electrical or Computer Engineering required with at least 10 years of experience.
Prior experience in post-silicon debug experience from first silicon to production
Prior experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan.
Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime
Prior experience working with Gate level simulation, debugging with VCS and other simulators.

Nice To Haves

Verilog design experience - developing custom DFT logic & IP integration; familiarity with functional verification
DFT CAD development - Test Architecture, Methodology and Infrastructure
Test Static Timing Analysis
Post silicon validation using DFT patterns.
Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design

Responsibilities

Responsible for defining and implementing post-silicon strategies
Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs.
Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL.
Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows.
Participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies.
Craft solutions and debug with minimal mentorship.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)