ASIC Design Verification Engineer, Technical Leader
About The Position
The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.
Requirements
- Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required
- Prior experience with System Verilog and UVM methodology
- Prior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoC
- Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
- Prior experience with functional coverage and constrained random DV environments.
- Scripting skills: Perl and/or Python scripting
Nice To Haves
- Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
- Experience with Veloce/HAPS is a plus
- Formal verification (iev/vc formal) knowledge is a plus
Responsibilities
- Maintaining existing DV environments and enhancing them
- Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop test cases, debug regression failures and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage
- Use AI tools to develop innovative methods and processes to improve quality of design verification.
Benefits
- medical, dental and vision insurance
- a 401(k) plan with a Cisco matching contribution
- paid parental leave
- short and long-term disability coverage
- basic life insurance
- grants of Cisco restricted stock units
- 10 paid holidays per full calendar year
- 1 floating holiday for non-exempt employees
- 1 paid day off for employee’s birthday
- paid year-end holiday shutdown
- 4 paid days off for personal wellness
- 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees (non-exempt)
- flexible vacation time off program (exempt)
- 80 hours of sick time off provided on hire date and each January 1st thereafter
- up to 80 hours of unused sick time carried forward from one calendar year to the next
- Additional paid time away may be requested to deal with critical or emergency issues for family members
- Optional 10 paid days per full calendar year to volunteer
- annual bonuses (for non-sales roles)
- performance-based incentive pay (for sales roles)
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What This Job Offers
Job Type
Full-time
Career Level
Senior
