ASIC DFT STA Technical Lead

Cisco•San Jose, CA

2d•$168,800 - $241,200

About The Position

You will be in the Silicon One development organization as an ASIC DFT STA Technical Lead. You are a detail-oriented STA engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate with cross-functional teams, communicate complex timing data clearly. As a member of this team, you will also be involved in crafting groundbreaking next generation networking chips. You will help lead to drive the DFT and quality process through the entire implementation flow and post silicon validation phases with additional exposure to physical design signoff activities.

Requirements

Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
Prior working experience with RTL design, CDC/RDC and conformal verification, SDC development.
Prior working experience in timing constraint development and verification.
Prior programming experience with at least 2 or more of the following scripting languages: Perl, TCL, Python, or Makefile.

Nice To Haves

Masters degree + 15+ years experience.
Prior working experience in debugging and analyzing PCIE timing constraints, TSMC memory timing constraints.
Prior working experience with RTL design, CDC/RDC and conformal verification.
Prior working experience in debugging and analyzing timing constraints, timing closure of DFT modes such as scan shift/capture and BIST.
Prior working experience with SDC debugging & STA tools like Synopsys TCM/Primetime.
Prior working experience with synthesis tools: Synopsys Fusion/design Compiler.
Prior working experience with Tessent tool like DFT insertion in RTL.

Responsibilities

Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs.
Check timing for unconstrained endpoints, no clock, etc.
SDC validation, CDC delay check, and SDC flow development.
Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy.

Benefits

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year
1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
16 days of paid vacation time per full calendar year (non-exempt)
flexible vacation time off program (exempt)
80 hours of sick time off provided on hire date and each January 1st thereafter
up to 80 hours of unused sick time carried forward
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses (for non-sales roles)
performance-based incentive pay (for sales roles)