ASIC Engineer - SDC

Cisco•San Jose, CA

4d•$165,000 - $241,400•Onsite

About The Position

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs. Drive Static Timing Analysis (STA) and partner with RTL, physical design, and DFT teams to resolve timing issues across the design hierarchy. Partner with RTL designers to achieve timing convergence through constraint development and timing-driven RTL improvements. Define and maintain clocking architectures and constraint models, including clock groups, timing exceptions, and clock exclusivity. Integrate and validate timing constraints from third-party IP vendors within the full-chip SoC timing environment. Develop and review block-level SDCs and clocking architectures, ensuring constraint correctness and alignment across the design hierarchy. Contribute to timing closure and silicon readiness across multiple modes, corners, and operating conditions.

Requirements

Bachelor’s degree in Electrical or Computer engineering and 7+ years of ASIC experience, or Master’s degree in Electrical Engineering or Computer Engineering and 4+ years of ASIC experience, or PhD in Electrical Engineering or Computer Engineering +1 years of ASIC experience.
Experience developing block-level and full-chip SDC constraints for complex SoC designs.
Expertise in Static Timing Analysis (STA) using tools such as Synopsys PrimeTime or Cadence Tempus.
Experience writing timing constraints for complex networking SoCs and ARM CPU subsystems.
Experience integrating third-party IP timing constraints into full-chip SDC environments.
Understanding with RTL design and synthesis, with the ability to analyze RTL structures and guide timing-driven design improvements.

Nice To Haves

Experience developing constraints for large SoCs with multiple clock domains and complex clocking architectures.
Ability to analyze RTL structures and recommend timing-driven micro-architectural improvements.
Expertise with constraint analysis tools (Synopsys TCM, Cadence CCD) and CDC analysis tools (SpyGlass CDC).
Proficiency in engineering scripting and automation (Python, Perl, TCL).

Responsibilities

Own and develop full-chip timing constraints (SDC) across functional and test modes for complex networking SoCs.
Drive Static Timing Analysis (STA) and partner with RTL, physical design, and DFT teams to resolve timing issues across the design hierarchy.
Partner with RTL designers to achieve timing convergence through constraint development and timing-driven RTL improvements.
Define and maintain clocking architectures and constraint models, including clock groups, timing exceptions, and clock exclusivity.
Integrate and validate timing constraints from third-party IP vendors within the full-chip SoC timing environment.
Develop and review block-level SDCs and clocking architectures, ensuring constraint correctness and alignment across the design hierarchy.
Contribute to timing closure and silicon readiness across multiple modes, corners, and operating conditions.

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