ASIC Engineer, Implementation - Timing

Meta•Austin, TX

3d•$146,000 - $209,000

About The Position

Meta's Silicon Engineering team is building custom silicon solutions that power the infrastructure behind Meta's AI and data center workloads at scale. As an ASIC Engineer focused on Implementation, you will drive the physical realization of complex custom chips from RTL through tapeout, working across synthesis, place-and-route, timing closure, and signoff. In this role, you will collaborate with architecture, design, and verification teams to deliver high-performance, power-efficient silicon that meets aggressive PPA targets for Meta's next-generation infrastructure platforms.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of experience with Timing Analysis
Experience with developing full chip flat & hierarchical timing constraints
Experience with AOCV/POCV timing analysis , SI noise analysis
Experience with running Static Timing Analysis for full chip using DMSA
Knowledge of front-end and back-end ASIC flows
Experience with communicating across functional internal teams and vendors

Nice To Haves

Experience with SOC Design Integration & Front End Implementation
Experience with Back End PD tools such as Fusion Compiler, Innovus
Experience with Front End Synthesis tools such as Design Compiler, Genus

Responsibilities

Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC.
Analyze the inter-block timing and come up with IO budgets for the various partition blocks.
Develop SOC Timing Full chip Flat & Hierarchical Constraints for Functional & DFT Modes.
Perform STA for full chip and Physical partition blocks using PrimeTime.
Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power.
Developing Automation scripts and Methodology for all FE-tools including (Synthesis, STA).
Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks.
Interact with Physical Design Engineers and provide them with timing/congestion feedback.