ASIC EDA Infrastructure Engineer Intern

Meta•Sunnyvale, CA
•$6,660 - $12,014

About The Position

Meta is hiring ASIC EDA Infrastructure Engineer Interns within its Infrastructure ASIC organization. The team builds EDA flows, automation, and infrastructure that support efficient System on Chip (SoC) and IP designs for data center applications. The intern will work with experienced engineers on a scoped project that contributes to how ASIC design teams build silicon, with mentorship, onboarding support, and regular feedback throughout the 12-week internship.

Requirements

  • Currently enrolled in a B.S. degree program in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
  • Coursework or project exposure to digital design or ASIC design fundamentals.
  • Exposure to RTL design using SystemVerilog, Verilog, or another HDL.
  • Programming or scripting experience in Python, with exposure to Tcl or shell scripting.
  • Interest in developer tooling, automation, build systems, or compute infrastructure.
  • Ability to communicate technical work clearly and collaborate across teams.
  • Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.
  • Intent to return to a full-time degree program after completing the internship.

Nice To Haves

  • Hands-on exposure to industry EDA tools through coursework, a lab or research project, a tapeout or design competition, or a prior internship.
  • Experience building automation, scripts, or developer tooling in a team or open-source setting.
  • Familiarity with version control (Git/Mercurial) and continuous integration concepts.
  • Exposure to Linux environments, job scheduling, or distributed compute.
  • Demonstrated focus on user experience and customer-oriented solutions.

Responsibilities

  • Contribute to the development and testing of front-end or physical design implementation flows.
  • Help build or improve internal automation tools that increase productivity across ASIC design cycles, such as RTL generation, memory selection automation, register generation, or filelist generation.
  • Write and maintain scripts that support day-to-day design flow tasks.
  • Help document EDA flows, tool behavior, and evaluation findings for the team.
  • Partner with internal infrastructure teams on compute grid, storage, and job scheduling efficiency.
  • Support efforts to adapt Meta infrastructure to ASIC design needs, including source control, continuous integration, data management, and reporting.
  • Present project results and recommendations to the team at the end of the internship.

Benefits

  • Benefits are offered; specific benefits are not listed.
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