ASIC DFT CAD Technical Leader

Cisco • San Jose, CA

8d

About The Position

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.

Requirements

• 8+ years of experience in DFT, CAD, or test automation for semiconductor designs.
• Prior experience with EDA DFT toolchain like Synopsys TestMAX, Synopsys VCS, Siemen's Tessent and similar,
• Experience in Tcl, Python, Perl, and shell scripting.
• Experience building automated flows and regression systems in compute farm environments (LSF/ or similar)
• Prior experience with SoC integration and cross-functional workflows.
• Experience applying AI/ML techniques to EDA workflows (log analysis, anomaly detection, predictive insights).

Nice To Haves

• Familiarity with data analytics tools (Python/pandas, dashboards, visualization tools).
• Experience with large-scale regression systems and distributed job management.
• Exposure to ATE/tester formats (e.g., STIL) and silicon bring-up/debug.

Responsibilities

• Own and drive end-to-end DFT flow architecture.
• Build and maintain scalable DFT CAD infrastructure from RTL ‚ DFT insertion, ATPG, simulation, reporting.
• Develop robust regression frameworks (LSF/cluster-based) with job orchestration, monitoring, logging, and failure recovery.
• Lead AI-driven automation initiatives for log analysis, failure triage, regression optimization, and intelligent debug.
• Collaborate with RTL, Physical Design, and Validation teams to ensure seamless DFT integration and signoff.
• Define and track key metrics (coverage, pattern count, runtime, regression health) and build dashboards for visibility.
• Standardize flows, improve reusability, and enforce best practices across projects.
• Evaluate and integrate new tools, methodologies, and AI technologies into existing flows.
• Mentor and guide engineers, driving technical excellence and innovation within the team.

Benefits

• medical, dental and vision insurance
• a 401(k) plan with a Cisco matching contribution
• paid parental leave
• short and long-term disability coverage
• basic life insurance
• Cisco restricted stock units
• 10 paid holidays per full calendar year
• 1 floating holiday for non-exempt employees
• 1 paid day off for employee’s birthday
• paid year-end holiday shutdown
• 4 paid days off for personal wellness
• 16 days of paid vacation time per full calendar year (non-exempt employees)
• flexible vacation time off program (exempt employees)
• 80 hours of sick time off provided on hire date and each January 1st thereafter
• up to 80 hours of unused sick time carried forward from one calendar year to the next
• Additional paid time away may be requested to deal with critical or emergency issues for family members
• Optional 10 paid days per full calendar year to volunteer
• annual bonuses (for non-sales roles)

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed