DFT Engineer

Broadcom•San Jose, CA

1d•Onsite

About The Position

Broadcom's ASIC Product Division is seeking candidates for a DFT position at our San Jose, California, Development Center. The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Products Division)’s designs – Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. It is expected that you can code using TCL, PERL, RUBY, PYTHON, C++ or similar.

Requirements

Exposure to DFT flows
Experience in Verilog coding, testbench generation and simulation
Memory BIST insertion and verification experience on embedded (SRAM, CAM, eDRAM, ROM)
Basic knowledge of Test-STA and constraints
Strong background on IEE1687, IJTAG, ICL and PDL
The ability to work in a multi-disciplined, cross-department environment
Solid knowledge in analog and digital circuit design, and device physics fundamentals
Good understanding of Si processing, logical and physical synthesis, and transistor reliability principles
Excellent problem solving, debug , root cause analysis and communication skills

Nice To Haves

Experience working on the ATE is a plus

Responsibilities

Understanding Broadcom and customer DFT feature requirements and DPPM goals and defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Generating, Verifying and Debugging Test vectors before tape release.
Validating and Debugging Test vectors on ATE during the silicon bring up phase
Assisting with silicon failure analysis, diagnostics and yield improvement efforts
Automating DFT and Test Vector Generation flows