ASIC Design Verification Engineer (Santa Clara, CA)
About The Position
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. This is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer. The team is responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support. The responsibility of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware UPF verification flow and methodology. Involve in developing automation to improve verification efficiency.
Requirements
- Minimum 3 years of DV experience using uvm/assertion based verification technologies
- Experience in verifying complex SOC or SOC subsystems
- Experience with caches and DDR memory protocol verification
- Experience with using memory verification VIP's
- Exposure to DDR phy
- Exposure to firmware/driver development using c++
- Exposure with multiple successful tapeouts from conception to post silicon debug
- Exposure to Formal verification
- Exposure to PASIM simulations
- Exposure to perf and power verification
- Skill proficiency: UVM, system verilog, assertion, C++, python
- Technology: DDR, CACHE, SOC
- Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
- PhD in Science, Engineering, or related field.
Responsibilities
- Comprehensive pre-silicon test planning for digital power IP's
- Testbench development using advanced verification methodology such as SystemVerilog-UVM
- Coverage development
- Assertion model development
- Formal verification (property checking)
- Learn and deploy power-aware UPF verification flow and methodology
- Develop automation to improve verification efficiency
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package
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What This Job Offers
Job Type
Full-time
Career Level
Entry Level
