Digital Design Engineer

Phizenix • Santa Clara, CA

1d • $180,000 - $250,000

About The Position

We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon. You will translate micro-architecture into clean, high-quality RTL and drive it through synthesis and timing closure. Just as important, the ideal candidate leverages strong firmware coding experience to drive pre-silicon simulation, develop bare-metal diagnostics, and ensure seamless hardware-software integration—for example, writing firmware on an embedded RISC CPU IP to control on-chip analog hardware blocks and low-speed control/calibration loops for optical components. Strong digital ASIC fundamentals, paired with the ability to debug complex designs in emulation and on silicon, round out the profile.

Requirements

• B.S. or M.S. in Electrical/Electronics or Computer Engineering (or related), with relevant digital ASIC design experience.
• Demonstrated experience taking digital designs from RTL through synthesis, timing closure, and silicon bring-up.
• Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods.
• Firmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g., RISC-V or Arm) to drive analog blocks and low-speed loops.
• Knowledge of AMBA and serial protocols, processors, and silicon bring-up sequences.
• Strong design, emulation, and silicon debug skills, with proven hardware-software integration experience.
• Expertise in synthesis, constraints, timing closure, and equivalence checks (Formality / Conformal).
• Experience with Lint / CDC / RDC tools.
• Customer-support orientation and excellent communication and oratory skills.

Nice To Haves

• Familiarity with interconnect protocols such as PCIe (Gen5/6/7) and UCIe.
• Experience integrating vendor CPU IP and developing the associated firmware, drivers, and diagnostics.
• High-speed wireline / SerDes-based SoC experience; UPF low-power design, DFT, and scan/ATPG flows.
• Scripting proficiency (Python, Tcl)

Responsibilities

• Develop micro-architecture and author high-quality, synthesizable RTL following best-in-class coding methods and design-for-verification / design-for-test practices.
• Write firmware and bare-metal diagnostics on embedded RISC CPU IP to configure and control on-chip analog blocks and low-speed control/calibration loops for optical components.
• Drive pre-silicon simulation and hardware-software co-verification, validating firmware against RTL well ahead of tape-out.
• Integrate processor subsystems—including licensed CPU IP—AMBA fabrics, and serial/interconnect interfaces (e.g., PCIe, UCIe) into the SoC/ASIC.
• Drive the full implementation flow: synthesis, timing constraints (SDC), timing closure, and equivalence checking (Formality / Conformal), with clean Lint / CDC / RDC signoff.
• Build and run emulation environments; lead silicon bring-up sequences and post-silicon debug, root-causing and resolving issues on hardware.
• Provide responsive support—triaging design problems and delivering timely solutions—and collaborate with analog/mixed-signal, DSP, verification, and physical-design teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior