Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Within this role, you'll work on closing timing at block, sub-chip, and full-chip levels, performing quality checks such as setup, hold, transition, and noise, while handling ECO tasks. As an ASIC Design Engineer on the STA team, you will play a pivotal role in extraction and static timing analysis (STA) flow development, convergence strategies, and correlation between PNR, Spice, and STA, while working alongside the Physical Design team.
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Job Type
Full-time
Career Level
Senior