Architect

Delos Data Inc•Palo Alto, CA

7d•$160,000 - $280,000

About The Position

The ASIC Architect will define, architect, and guide development of next-generation, high-performance ASICs. The role translates high-level system requirements into detailed architectural specifications while balancing power, performance, and area (PPA) trade-offs. It covers IP blocks, subsystems, and full SoC integration for advanced AI accelerators, networking, and datacenter computing workloads. The architect works across design and implementation teams, leads architectural reviews and trade-off studies, and provides technical leadership and mentorship.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science.
At least 7 years of experience in ASIC architecture, micro-architecture, or high-level design.
Strong proficiency in SystemVerilog/Verilog and C/C++ or SystemC for modeling.
Deep knowledge of computer architecture, including CPU/GPU cores, caches, fabric, and memory hierarchies.
Experience with industry-standard protocols such as Ethernet, PCIe, or UAL.
Familiarity with EDA tools such as Synopsys Design Compiler, Cadence Genus, or similar.
Experience with performance modeling and analysis tools.

Nice To Haves

Master’s degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
Experience designing AI/ML accelerators or high-performance networking silicon.
Proven record of shipping high-performance silicon from concept to tape-out.
Familiarity with pre-silicon emulation platforms.
Strong scripting skills in Python, Tcl, or Perl for automation.
Excellent communication skills and ability to articulate complex architectural concepts.
Proactive problem solver capable of working with minimal oversight.
Strong leadership and mentorship capabilities.

Responsibilities

Lead creation of Architectural Design Specifications (ADS) and Micro-architecture Specifications (MAS) for complex ASICs, including high-speed interconnect fabric and IO protocols such as Ethernet, PCIe, and UCIe.
Develop high-level performance models using SystemC/TLM, C++, or Python to analyze workload behavior and validate architectural assumptions.
Optimize chip-level and block-level architecture to meet power, performance, and area goals.
Partner with RTL design, verification, physical design, firmware, and software teams to support implementation and validation.
Drive architectural trade-off studies and lead design reviews.
Define power management strategies, including DVFS, power domains, and clock gating.
Mentor junior engineers and contribute to technical leadership across the organization.