Analog Layout Engineer - Senior Consultant

Redolent • San Jose, CA

5d • Onsite

About The Position

Our direct client is urgently looking for an Analog Layout Engineer in San Jose, CA. This is a contracting position for six months with possible extension. The role requires experience in 16nm TSMC, 14nm, or 22nm Intel processes. The senior layout designer will be responsible for the layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc. Responsibilities include leading IC layout of cutting-edge high performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry. This is an onsite role.

Requirements

• 10+ years experience in high-performance analog layout in advanced CMOS processes.
• Thorough knowledge of industry-standard EDA tools from Cadence, Mentor, and Synopsys.
• Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
• Demonstrated experience with the analog layout for silicon chips in mass production.
• Self-starter with the ability to define and adhere to a schedule.
• Must possess strong written and verbal communication skills.

Nice To Haves

• Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc.
• Experience with FinFET process nodes preferred.
• Experience working with distributed design teams is a plus.
• Knowledge of skill code layout automation is a plus.

Responsibilities

• Leading IC layout of cutting-edge high performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.
• Layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
• Floor planning, block-level routing, and top-level chip assembly.
• Applying high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
• Defining and adhering to a schedule.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed