Principal Analog Layout Engineer
About The Position
Marvell Central Engineering (CE) develops Marvell's most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production. Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. This is a rare foundational engineering opportunity as part of our strategic expansion into Southern California. You will help shape the technical DNA and culture of Marvell's San Diego design organization.
Requirements
- Experienced in Cadence “Virtuoso VXL” and/or Synopsys “Custom Compiler” layout tools.
- Experienced in Mentor Graphics “Calibre” drc/lvs verification tool.
- Good problem-solving skills.
- Strong communication and presentation skills.
- Ability to work independently as well as in teams, including remote design teams.
- Ability to work across functions and levels.
- Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience.
- Master’s degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience.
- PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience.
Responsibilities
- Drawing layouts for schematics created by Circuit Design Engineers, using industry standard CAD tools, in deep sub-micron, FinFET technologies.
- Effectively communicate with Design Engineers to clarify and realize the layout requirements based on the schematic functions.
- Provide feedback to Circuit Design Engineers on any modifications to schematics after layouts are completed.
- Interact with Physical Verification (PV) team to analyze DRC, LVS, ANT, ERC, and EMIR results and achieve PV closure.
- Adhere to Marvell’s core behaviors and strive to continuously improve your skills as an Analog Layout Engineer.
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs to help balance work and home life
- robust mental health resources to prioritize emotional well-being
- recognition and service awards to celebrate contributions and milestones
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Principal
Education Level
Ph.D. or professional degree
