Analog Design Engineer (TERADYNE, Agoura Hills, CA)

Teradyne•Agoura Hills, CA

About The Position

Teradyne’s Semiconductor Test Division in Agoura Hills, California, is seeking an Analog Design Engineer to develop high-speed analog and mixed-signal ASICs for Automatic Test Equipment (ATE). The role involves designing and simulating CMOS circuits, supporting ASIC integration and validation, and collaborating with engineers across analog and digital design, verification, validation, test, product, and EDA. The engineer will also develop automation and explore AI-enabled tools to improve design and engineering workflows. This position offers the opportunity to build technical expertise alongside experienced engineers throughout the IC development lifecycle. The ideal candidate is curious, analytical, collaborative, and motivated to grow their semiconductor design expertise. The position is eligible for discretionary bonuses based on financial performance. Teradyne offers medical, dental, and vision coverage; Flexible Spending Accounts; retirement savings plans; life and disability insurance; paid vacation and holidays; tuition assistance; and other benefits.

Requirements

Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
At least 2 years of relevant industry experience in analog or mixed-signal IC design, simulation, or characterization.
Hands-on experience with CMOS analog or mixed-signal circuit design and simulation.
Working knowledge of common analog and mixed-signal circuit architectures, potentially including PLLs, DLLs, ADCs, DACs, VCOs, CDRs, amplifiers, clocking circuits, high-speed I/Os, or CML circuits.
Understanding of CMOS device fundamentals, semiconductor processes, PDKs, and PVT effects.
Experience with industry-standard IC design and simulation tools, preferably Cadence.
Experience with scripting or programming languages such as Python, SKILL, or Ocean for engineering automation or data analysis.
Strong analytical and problem-solving skills and ability to work effectively in a collaborative engineering environment.
Strong written and verbal communication skills.

Nice To Haves

Experience supporting one or more ASICs through tape-out, silicon bring-up, characterization, or production test.
Familiarity with advanced semiconductor technologies, including FinFET processes at 16nm or below.
Exposure to high-frequency or high-speed analog and mixed-signal design.
Experience with laboratory characterization and test equipment.
Familiarity with Verilog or Verilog-A.
Exposure to AI/ML, generative AI, or large-scale data analysis applied to semiconductor design, verification, validation, or test.
Interest in using emerging technologies and automation to improve semiconductor engineering workflows.

Responsibilities

Design, simulate, and optimize high-speed analog and mixed-signal circuits from specification through transistor-level implementation.
Perform circuit-level verification and simulation across process, voltage, and temperature (PVT) corners using Cadence EDA tools.
Support schematic, layout, physical verification, and ASIC integration activities in collaboration with the design team.
Participate in design reviews and contribute to circuit analysis, debugging, and technical problem-solving.
Support silicon characterization, laboratory measurements, debug, validation, and production test activities.
Analyze simulation and laboratory data to identify performance trends and design improvements.
Develop and maintain scripts and automation tools to improve simulation, verification, characterization, and data analysis workflows.
Explore AI-assisted engineering tools and methodologies to improve design productivity and analysis.
Collaborate with analog, digital, validation, test, product, and EDA engineers throughout the IC development lifecycle.
Maintain clear technical documentation and communicate design results, issues, and recommendations to the broader engineering team.