Analog Circuit Design Engineer

Intel CorporationSanta Clara, CA
$164,470 - $232,190Hybrid

About The Position

We are seeking a highly motivated Analog Circuit Design Engineer with a strong interest in power delivery circuits and architectures. In this role, you will design and develop advanced analog and mixed-signal circuits for integrated voltage regulation and power management IPs that are critical to Intel's products. You are passionate about solving complex challenges in power integrity, efficiency, transient response, and low-noise design, and thrive in collaborative, fast-paced environments.

Requirements

  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 6+ years of experience, OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 4+ years of experience, OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field with 2+ years of experience
  • Experience in analog or mixed-signal circuit design (Amplifiers, LDOs, PLLs, ADCs, etc.)
  • Experience taking designs from circuit to layout to silicon prototype
  • Strong background in VLSI and industry-standard CAD tools for schematic and simulation, such as Cadence Spectre, AMS Designer, Virtuoso, and StarRC

Nice To Haves

  • Knowledge of Power Delivery, Power Management systems, or PMIC
  • Experience in mixed-signal modeling and system analysis of complex feedback systems

Responsibilities

  • Design and develop analog and mixed-signal ICs for power delivery IPs, including IVRs, LDOs, DC-DC converters, and power gating circuits
  • Perform transient, AC, and noise simulations to evaluate stability, load regulation, droop response, and PSRR
  • Analyze and optimize power delivery performance, including efficiency, transient response, and power integrity
  • Conduct tradeoff analysis across power, performance, area, bandwidth, and quiescent current
  • Create floorplans and guide layout with attention to matching, parasitics, current density, and clean power routing
  • Perform power integrity analysis including IR drop, decoupling strategies, and package interaction effects
  • Collaborate with architecture, digital, layout, and platform teams to ensure robust power delivery integration
  • Develop and execute validation test plans to verify design performance against specifications
  • Support post-silicon bring-up, characterization, and debug of power delivery circuits
  • Document design methodologies, specifications, and validation results
  • Participate in design reviews and contribute to next-generation power delivery innovations

Benefits

  • competitive pay
  • stock bonuses
  • health
  • retirement
  • vacation
© 2026 Teal Labs, Inc
Privacy PolicyTerms of Service