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Advanced Micro Devices, Inc•Austin, TX

39d•Hybrid

About The Position

AMD is seeking an experienced Test Engineer to lead the architecture, development, and integration of wafer-sort test infrastructure on Advantest V93000 platforms using SmarTest 8. You will contribute to AMD’s common Base Test Program and Test Shell while leading or co-leading test enablement for high-speed I/O and die-to-die interfaces. This role combines hands-on test program development with technical leadership across Product Engineering, Design for Test, Test Engineering, Yield Engineering, Test Hardware, and Manufacturing. Your work will improve test quality, yield, test time, scalability, and release readiness for modern microprocessor and chiplet-based products.

Requirements

Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Typically, seven or more years of semiconductor product-development and ATE test-engineering experience.
This role is not eligible for visa sponsorship.

Nice To Haves

Extensive Advantest V93000 test program development and debug experience.
SmarTest 8 test program development and debug experience.
Proficiency in Java and at least one additional programming or scripting language, such as C++, Python, Perl, or shell scripting.
Experience developing test flows, test methods, patterns or vectors, timing, levels, diagnostics, characterization plans, and manufacturing screens.
Experience debugging hardware, software, device, and manufacturing interactions within wafer-sort or final-test environments.
Linux or Unix proficiency, including experience with revision control and disciplined software-release practices.
Experience with ORE or comparable offline simulation, including leading the development, debug, and validation of test program content offline and using tester access only when necessary.
Experience leading, co-owning, or making significant architectural contributions to a Base Test Program, common Test Shell, or comparable shared ATE infrastructure.
Experience with high-speed SerDes PHY validation, characterization, margining, link training, equalization, and failure analysis.
Knowledge of PCI Express, Compute Express Link, Universal Chiplet Interconnect Express, Ethernet, JESD204, USB, DDR, HBM PHY, or comparable high-speed serial, memory, or die-to-die interfaces.
Experience with source-synchronous interface testing, forwarded-clock architectures, clock and data timing margining, lane-level diagnostics, repair or redundancy, and multi-lane link debug.
Experience with bit-error-rate testing, jitter and timing analysis, voltage margining, eye-related measurements, and correlation across ATE, bench, and system environments.
Knowledge of chiplet, 2.5D/3D packaging, interposer, bridge, advanced-packaging test challenges, and known-good-die considerations.
Experience with coherent or fabric interconnect technologies such as Compute Express Link, Universal Chiplet Interconnect Express, xGMI/Infinity Fabric, UPI, NVLink, or comparable technologies.
Experience using AI and developing agentic workflows to improve test program development, debug, validation, documentation, and engineering productivity.
Expertise with Jira and Confluence—or comparable platforms such as Azure DevOps, GitHub, or GitLab—for release planning, task tracking, dependency management, issue tracking, workflow automation, and engineering documentation.
Strong communication skills and demonstrated ability to lead and collaborate with geographically distributed engineering teams.

Responsibilities

Contribute to the architecture, development, and integration of the wafer-sort Base Test Program and common Test Shell, including reusable services, configurations, test flows, diagnostics, data collection, release controls, and product-integration interfaces.
Lead SmarTest 8 and Advantest V93000 test program infrastructure development, debug, validation, release readiness, and production support.
Define scalable architecture and coding practices that enable reuse across products, derivatives, silicon revisions, test insertions, and manufacturing sites.
Lead or co-lead wafer-sort test strategy, first-silicon bring-up, characterization, margining, screening, diagnostics, and failure isolation for high-speed I/O and die-to-die interfaces.
Integrate patterns, vectors, timing, levels, test methods, device configurations, binning, data collection, and debug capabilities into the common test program.
Debug complex interactions across silicon, test software, tester hardware, probe hardware, patterns, timing, and manufacturing processes.
Partner with Design, Design for Test, Product Engineering, Yield Engineering, Test Hardware, and Manufacturing teams to identify coverage gaps, improve testability, and resolve product and production risks.
Drive improvements in test quality, manufacturing yield, test time, maintainability, correlation, and release discipline.
Lead technical reviews, document architectural decisions, mentor engineers, and influence infrastructure direction across project and functional boundaries.
Support geographically distributed engineering teams, outsourced semiconductor assembly and test partners, and equipment vendors throughout development and high-volume manufacturing.