AI Hardware Engineering Intern

Intel•Folsom, CA

18h•Hybrid

About The Position

Intel is seeking a student intern to research the future of AI inference and AI infrastructure, with an emphasis on hardware/software co-design. The role examines how model architecture, inference behavior, memory movement, data-center constraints, and software stacks affect customer outcomes such as throughput, latency, time-to-first-token, tokens per second, power consumption, utilization, total cost of ownership, and deployability. The intern will conduct independent technical research and analysis while working with a technical team of researchers and engineers on AI hardware and infrastructure challenges. The work spans AI infrastructure components and software layers, including CPUs, GPUs, AI accelerators, ASICs, memory systems, networking, storage, rack-scale architecture, power delivery, cooling, cluster management, firmware, compilers, kernels, and serving stacks. The intern will analyze generative and agentic AI workloads, investigate inference pipeline behavior and system bottlenecks, and develop technical recommendations for Intel based on customer use cases, workload performance, and ML systems research. The position also supports silicon hardware programs through phases of the silicon lifecycle, from concept to silicon, and may involve subsystem or top-level ASIC and SoC design considerations. The intern will benchmark and compare hardware and infrastructure approaches; develop models, simulations, prototypes, or analysis tools; work with Intel teams and external software ecosystem partners to understand requirements and bottlenecks; and present findings through architecture diagrams, benchmark analyses, technical reports, design recommendations, and presentations. The role is hybrid, with an assigned Intel site in California.

Requirements

Currently pursuing a PhD in Computer Science, Computer Engineering, Electrical Engineering, AI/ML, Systems Engineering, or a related technical discipline.
Strong foundation in computer architecture, operating systems, distributed systems, parallel computing, AI/ML systems, high-performance computing, or systems software.
Familiarity with generative AI models and inference concepts, including transformers, attention, token generation, model serving, quantization, batching, KV cache, long-context workloads, and latency-throughput trade-offs.
Programming experience in one or more of C, C++, Rust, CUDA, SYCL, OpenCL, or a comparable low-level or performance-oriented language.
Cumulative GPA of 3.0 or higher.
Expertise in modern high-performance CPU, GPU, or AI accelerator architecture and hardware/software interactions.
Good understanding of firmware codebases, compilers, kernels, serving stacks, and model architectures.
Good understanding of silicon design for ASIC and SoC subsystems or top-level functions, from architecture specification to production silicon, including memory subsystems and interconnects.

Nice To Haves

Coursework, research, or project experience in computer architecture, VLSI, digital design, ASIC/FPGA systems, compilers, kernel development, GPU programming, distributed systems, high-performance computing, or AI systems.
Experience using profiling, tracing, or benchmarking tools to evaluate CPU, GPU, accelerator, network, memory, storage, or software performance.
Familiarity with AI hardware platforms such as Intel Xeon processors, Intel GPUs, NVIDIA GPUs, AMD GPUs, TPUs, custom AI accelerators, FPGAs, or domain-specific inference ASICs.
Understanding of memory hierarchies and performance concepts, including cache behavior, DRAM, HBM, memory bandwidth, memory capacity, latency, data locality, DMA, and data movement.
Experience with inference frameworks or runtimes such as vLLM, SGLang, Hugging Face Transformers, PyTorch, Triton, or Ray.
Familiarity with AI systems infrastructure such as Linux, containers, Kubernetes, distributed storage, RDMA over Ethernet, InfiniBand, CXL, PCIe, NVMe, UALink/eSUN-based interconnects, silicon photonics, and cluster-management software.
Some experience with simulation, modeling, emulation, RTL, FPGA prototyping, firmware, driver development, or low-level debugging.
Some experience contributing to open-source systems, ML infrastructure, compiler, kernel, framework, or performance-engineering projects.

Responsibilities

Conduct technical research on next-generation AI infrastructure, including processors, accelerators, memory, networking, storage, rack-scale architecture, power delivery, cooling, and cluster management.
Analyze generative AI and agentic AI workloads and their hardware implications, including transformer inference, mixture-of-experts, multimodal models, interactive inference, and distributed serving.
Evaluate AI inference pipeline behavior, including prefill and decode demands, memory capacity and bandwidth, KV-cache management, compute utilization, interconnect bandwidth, and latency.
Identify product and system gaps that may limit Intel’s ability to serve AI customers, including hardware, developer tooling, performance libraries, reference architectures, deployment models, observability, and ecosystem enablement.
Support silicon hardware programs through multiple phases of the silicon lifecycle, including end-to-end chip execution from concept to silicon.
Develop technical recommendations on what Intel should build, optimize, enable, or partner on to meet AI customer requirements.
Benchmark and compare AI hardware and infrastructure approaches across performance, power efficiency, cost, programmability, memory hierarchy, scalability, ecosystem maturity, and workload fit.
Develop technical models, simulations, prototypes, or analysis tools to evaluate hardware/software trade-offs for AI workloads.
Investigate bottlenecks across compute, memory, networking, storage, and software orchestration, and propose methods to improve end-to-end AI workload performance.
Work with Intel technical teams and external ISVs to collect information on model requirements, inference bottlenecks, deployment challenges, hardware optimization opportunities, and customer priorities.
Engage with AI software ecosystem partners, including model providers, inference-engine developers, cloud providers, framework teams, and ISVs, to understand how their stacks interact with hardware.
Present findings through architecture diagrams, benchmark analyses, technical reports, design recommendations, and executive-ready presentations.